[PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support

[PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
SPEAr13xx PCIe driver based on designware controller driver.

SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
with ahci/sata pins. By default evaluation board of both controller
works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the
necessary modifications on board and enable (okay) pcie and miphy
from respective evb dtsi file.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 arch/arm/boot/dts/spear1310.dtsi  |    6 +
 arch/arm/boot/dts/spear1340.dtsi  |    2 +
 arch/arm/boot/dts/spear13xx.dtsi  |    4 +-
 arch/arm/mach-spear/Kconfig       |    1 +
 drivers/pci/host/Kconfig          |    8 +
 drivers/pci/host/Makefile         |    1 +
 drivers/pci/host/pcie-spear13xx.c |  414 +++++++++++++++++++++++++++++++++++++
 7 files changed, 434 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/host/pcie-spear13xx.c

diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 136a12d..5c1a4d9 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -90,6 +90,8 @@
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0x0 0 &gic 68>;
 			num-lanes = <1>;
+			phys = <&miphy0 1>;
+			phy-names = "pcie-phy";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -106,6 +108,8 @@
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0x0 0 &gic 69>;
 			num-lanes = <1>;
+			phys = <&miphy1 1>;
+			phy-names = "pcie-phy";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -122,6 +126,8 @@
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0x0 0 &gic 70>;
 			num-lanes = <1>;
+			phys = <&miphy2 1>;
+			phy-names = "pcie-phy";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 9af299d..611f1f8 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -55,6 +55,8 @@
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0x0 0 &gic 68>;
 			num-lanes = <1>;
+			phys = <&miphy0 1>;
+			phy-names = "pcie-phy";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3a72508..a6eb543 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges = <0x50000000 0x50000000 0x10000000
-			  0xb0000000 0xb0000000 0x10000000
-			  0xd0000000 0xd0000000 0x02000000
+			  0x80000000 0x80000000 0x20000000
+			  0xb0000000 0xb0000000 0x22000000
 			  0xd8000000 0xd8000000 0x01000000
 			  0xe0000000 0xe0000000 0x10000000>;
 
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 29aee02..f335702 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -27,6 +27,7 @@ config ARCH_SPEAR13XX
 	select PINCTRL
 	select USE_OF
 	select MFD_SYSCON
+	select MIGHT_HAVE_PCI
 	help
 	  Supports for ARM's SPEAR13XX family
 
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..8697dd1 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,12 @@ config PCI_RCAR_GEN2
 	  There are 3 internal PCI controllers available with a single
 	  built-in EHCI/OHCI host controller present on each one.
 
+config PCIE_SPEAR13XX
+	tristate "STMicroelectronics SPEAr PCIe controller"
+	depends on ARCH_SPEAR13XX
+	select PCIEPORTBUS
+	select PCIE_DW
+	help
+	  Say Y here if you want PCIe support on SPEAr13XX SoCs.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..42a491d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
new file mode 100644
index 0000000..c70d526
--- /dev/null
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -0,0 +1,414 @@
+/*
+ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
+ *
+ * SPEAr13xx PCIe Glue Layer Source Code
+ *
+ * Copyright (C) 2010-2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ * Mohit Kumar <mohit.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include "pcie-designware.h"
+
+struct spear13xx_pcie {
+	void __iomem		*app_base;
+	struct phy		*phy;
+	struct clk		*clk;
+	struct pcie_port	pp;
+	bool			is_gen1;
+};
+
+struct pcie_app_reg {
+	u32	app_ctrl_0;		/*cr0*/
+	u32	app_ctrl_1;		/*cr1*/
+	u32	app_status_0;		/*cr2*/
+	u32	app_status_1;		/*cr3*/
+	u32	msg_status;		/*cr4*/
+	u32	msg_payload;		/*cr5*/
+	u32	int_sts;		/*cr6*/
+	u32	int_clr;		/*cr7*/
+	u32	int_mask;		/*cr8*/
+	u32	mst_bmisc;		/*cr9*/
+	u32	phy_ctrl;		/*cr10*/
+	u32	phy_status;		/*cr11*/
+	u32	cxpl_debug_info_0;	/*cr12*/
+	u32	cxpl_debug_info_1;	/*cr13*/
+	u32	ven_msg_ctrl_0;		/*cr14*/
+	u32	ven_msg_ctrl_1;		/*cr15*/
+	u32	ven_msg_data_0;		/*cr16*/
+	u32	ven_msg_data_1;		/*cr17*/
+	u32	ven_msi_0;		/*cr18*/
+	u32	ven_msi_1;		/*cr19*/
+	u32	mst_rmisc;		/*cr 20*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID			0
+#define TX_LANE_FLIP_EN_ID			1
+#define SYS_AUX_PWR_DET_ID			2
+#define APP_LTSSM_ENABLE_ID			3
+#define SYS_ATTEN_BUTTON_PRESSED_ID		4
+#define SYS_MRL_SENSOR_STATE_ID			5
+#define SYS_PWR_FAULT_DET_ID			6
+#define SYS_MRL_SENSOR_CHGED_ID			7
+#define SYS_PRE_DET_CHGED_ID			8
+#define SYS_CMD_CPLED_INT_ID			9
+#define APP_INIT_RST_0_ID			11
+#define APP_REQ_ENTR_L1_ID			12
+#define APP_READY_ENTR_L23_ID			13
+#define APP_REQ_EXIT_L1_ID			14
+#define DEVICE_TYPE_EP				(0 << 25)
+#define DEVICE_TYPE_LEP				(1 << 25)
+#define DEVICE_TYPE_RC				(4 << 25)
+#define SYS_INT_ID				29
+#define MISCTRL_EN_ID				30
+#define REG_TRANSLATION_ENABLE			31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID			2
+#define APPS_PM_XMT_PME_ID			5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
+#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
+#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
+#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
+#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
+#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
+#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
+#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
+#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
+#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
+#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
+#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
+#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
+#define XMLH_LTSSM_STATE_L0			0x11
+#define XMLH_LTSSM_STATE_L0S			0x12
+#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define XMLH_LTSSM_STATE_L1_IDLE		0x14
+#define XMLH_LTSSM_STATE_L2_IDLE		0x15
+#define XMLH_LTSSM_STATE_L2_WAKE		0x16
+#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
+#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
+#define XMLH_LTSSM_STATE_DISABLED		0x19
+#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
+#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
+#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
+#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
+#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
+#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
+#define XMLH_LTSSM_STATE_MASK			0x3F
+#define XMLH_LINK_UP				(1 << 6)
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID				18
+
+/*CR6*/
+#define INTA_CTRL_INT				(1 << 7)
+#define INTB_CTRL_INT				(1 << 8)
+#define INTC_CTRL_INT				(1 << 9)
+#define INTD_CTRL_INT				(1 << 10)
+#define MSI_CTRL_INT				(1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID				11
+#define VEN_MSI_FUN_NUM_ID			8
+#define VEN_MSI_TC_ID				5
+#define VEN_MSI_VECTOR_ID			0
+#define VEN_MSI_REQ_EN		((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK	((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK		((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK	((u32)0x1F << VEN_MSI_VECTOR_ID)
+
+#define PCI_CAP_ID_EXP_OFFSET			0x70
+
+#define to_spear13xx_pcie(x)	container_of(x, struct spear13xx_pcie, pp)
+
+static int spear13xx_pcie_establish_link(struct pcie_port *pp)
+{
+	u32 val;
+	int count = 0;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+
+	if (dw_pcie_link_up(pp)) {
+		dev_err(pp->dev, "Link already up\n");
+		return 0;
+	}
+
+	/* setup root complex */
+	dw_pcie_setup_rc(pp);
+
+	/*
+	 * this controller support only 128 bytes read size, however its
+	 * default value in capability register is 512 bytes. So force
+	 * it to 128 here.
+	 */
+	dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+	val &= ~PCI_EXP_DEVCTL_READRQ;
+	dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+
+	/* program vid and did for RC */
+	dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
+	dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
+
+	/*
+	 * if is_gen1 is set then handle it, so that some buggy card
+	 * also works
+	 */
+	if (spear13xx_pcie->is_gen1) {
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCAP, 4, val);
+		}
+
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCTL2, 4, val);
+		}
+	}
+
+	/* enable ltssm */
+	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+			| (1 << APP_LTSSM_ENABLE_ID)
+			| ((u32)1 << REG_TRANSLATION_ENABLE),
+			&app_reg->app_ctrl_0);
+
+	/* check if the link is up or not */
+	while (!dw_pcie_link_up(pp)) {
+		mdelay(100);
+		count++;
+		if (count == 10) {
+			dev_err(pp->dev, "Link Fail\n");
+			return -EINVAL;
+		}
+	}
+	dev_info(pp->dev, "Link up\n");
+
+	return 0;
+}
+
+static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
+{
+	struct pcie_port *pp = arg;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	unsigned int status;
+
+	status = readl(&app_reg->int_sts);
+
+	if (status & MSI_CTRL_INT) {
+		if (!IS_ENABLED(CONFIG_PCI_MSI))
+			BUG();
+		dw_handle_msi_irq(pp);
+	}
+
+	writel(status, &app_reg->int_clr);
+
+	return IRQ_HANDLED;
+}
+
+static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	/* Enable MSI interrupt */
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		dw_pcie_msi_init(pp);
+		writel(readl(&app_reg->int_mask) |
+				MSI_CTRL_INT, &app_reg->int_mask);
+	}
+
+	return;
+}
+
+static int spear13xx_pcie_link_up(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
+		return 1;
+
+	return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+	spear13xx_pcie_establish_link(pp);
+	spear13xx_pcie_enable_interrupts(pp);
+}
+
+static struct pcie_host_ops spear13xx_pcie_host_ops = {
+	.link_up = spear13xx_pcie_link_up,
+	.host_init = spear13xx_pcie_host_init,
+};
+
+static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	pp->irq = platform_get_irq(pdev, 0);
+	if (!pp->irq) {
+		dev_err(dev, "failed to get irq\n");
+		return -ENODEV;
+	}
+	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
+				IRQF_SHARED, "spear1340-pcie", pp);
+	if (ret) {
+		dev_err(dev, "failed to request irq\n");
+		return ret;
+	}
+
+	pp->root_bus_nr = -1;
+	pp->ops = &spear13xx_pcie_host_ops;
+
+	spin_lock_init(&pp->conf_lock);
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(dev, "failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __init spear13xx_pcie_probe(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie;
+	struct pcie_port *pp;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *dbi_base;
+	int ret;
+
+	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
+				GFP_KERNEL);
+	if (!spear13xx_pcie) {
+		dev_err(dev, "no memory for SPEAr13xx pcie\n");
+		return -ENOMEM;
+	}
+
+	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
+	if (IS_ERR(spear13xx_pcie->phy)) {
+		ret = PTR_ERR(spear13xx_pcie->phy);
+		switch (ret) {
+		case -EPROBE_DEFER:
+			dev_info(dev, "probe deferred\n");
+			return ret;
+		default:
+			dev_err(dev, "couldn't get pcie-phy\n");
+			return ret;
+		}
+	}
+
+	phy_init(spear13xx_pcie->phy);
+
+	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(spear13xx_pcie->clk)) {
+		dev_err(dev, "couldn't get clk for pcie\n");
+		return PTR_ERR(spear13xx_pcie->clk);
+	}
+	ret = clk_prepare_enable(spear13xx_pcie->clk);
+	if (ret) {
+		dev_err(dev, "couldn't enable clk for pcie\n");
+		return ret;
+	}
+
+	pp = &spear13xx_pcie->pp;
+
+	pp->dev = dev;
+
+	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
+	if (IS_ERR(pp->dbi_base)) {
+		dev_err(dev, "couldn't remap dbi base\n");
+		ret = PTR_ERR(pp->dbi_base);
+		goto fail_clk;
+	}
+	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
+
+	if (of_property_read_bool(np, "st,pcie-is-gen1"))
+		spear13xx_pcie->is_gen1 = true;
+
+	ret = add_pcie_port(pp, pdev);
+	if (ret < 0)
+		goto fail_clk;
+
+	platform_set_drvdata(pdev, spear13xx_pcie);
+	return 0;
+
+fail_clk:
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	return ret;
+}
+
+static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	phy_exit(spear13xx_pcie->phy);
+
+	return 0;
+}
+
+static const struct of_device_id spear13xx_pcie_of_match[] = {
+	{ .compatible = "st,spear1340-pcie", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
+
+static struct platform_driver spear13xx_pcie_driver = {
+	.probe		= spear13xx_pcie_probe,
+	.remove		= spear13xx_pcie_remove,
+	.driver = {
+		.name	= "spear-pcie",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
+	},
+};
+
+/* SPEAr13xx PCIe driver does not allow module unload */
+
+static int __init pcie_init(void)
+{
+	return platform_driver_register(&spear13xx_pcie_driver);
+}
+module_init(pcie_init);
+
+MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
-- 
1.7.0.1

[PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

[Mohit Kumar]

Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci@vger.kernel.org
---
 MAINTAINERS |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b2cf5cf..ebdca89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6596,6 +6596,12 @@ L:	linux-pci@vger.kernel.org
 S:	Maintained
 F:	drivers/pci/host/*designware*
 
+PCIE DRIVER FOR ST SPEAR13XX
+M:	Mohit Kumar <mohit.kumar@st.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	drivers/pci/host/pcie-spear13xx.c
+
 PCMCIA SUBSYSTEM
 P:	Linux PCMCIA Team
 L:	linux-pcmcia@lists.infradead.org
-- 
1.7.0.1

Re: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support

[Jingoo Han]

On Friday, February 28, 2014 8:55 PM, Mohit Kumar wrote:
> 
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
> SPEAr13xx PCIe driver based on designware controller driver.
> 
> SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
> with ahci/sata pins. By default evaluation board of both controller
> works for ahci mode.
> To use these patches on SPEAr1340/1310 evaluation board, do the
> necessary modifications on board and enable (okay) pcie and miphy
> from respective evb dtsi file.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>

For 'drivers/pci/host/pcie-spear13xx.c',

Reviewed-by: Jingoo Han <jg1.han@samsung.com>

Best regards,
Jingoo Han

> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
>  arch/arm/boot/dts/spear1310.dtsi  |    6 +
>  arch/arm/boot/dts/spear1340.dtsi  |    2 +
>  arch/arm/boot/dts/spear13xx.dtsi  |    4 +-
>  arch/arm/mach-spear/Kconfig       |    1 +
>  drivers/pci/host/Kconfig          |    8 +
>  drivers/pci/host/Makefile         |    1 +
>  drivers/pci/host/pcie-spear13xx.c |  414 +++++++++++++++++++++++++++++++++++++
>  7 files changed, 434 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/pci/host/pcie-spear13xx.c

RE: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support

[Mohit KUMAR DCG]

SGVsbG8gSmluZ29vLA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEpp
bmdvbyBIYW4gW21haWx0bzpqZzEuaGFuQHNhbXN1bmcuY29tXQ0KPiBTZW50OiBGcmlkYXksIE1h
cmNoIDE0LCAyMDE0IDExOjMyIEFNDQo+IFRvOiBNb2hpdCBLVU1BUiBEQ0cNCj4gQ2M6IGFybmRA
YXJuZGIuZGU7IFByYXR5dXNoIEFOQU5EOyAnVmlyZXNoIEt1bWFyJzsgc3BlYXItZGV2ZWw7IGxp
bnV4LQ0KPiBwY2lAdmdlci5rZXJuZWwub3JnOyAnSmluZ29vIEhhbicNCj4gU3ViamVjdDogUmU6
IFtQQVRDSCBWNyAwOC8xMF0gcGNpZTogU1BFQXIxM3h4OiBBZGQgZGVzaWdud2FyZSB3cmFwcGVy
DQo+IHN1cHBvcnQNCj4gDQo+IE9uIEZyaWRheSwgRmVicnVhcnkgMjgsIDIwMTQgODo1NSBQTSwg
TW9oaXQgS3VtYXIgd3JvdGU6DQo+ID4NCj4gPiBGcm9tOiBQcmF0eXVzaCBBbmFuZCA8cHJhdHl1
c2guYW5hbmRAc3QuY29tPg0KPiA+DQo+ID4gU1BFQXIxMzEwIGFuZCBTUEVBcjEzNDAgU09DIHVz
ZXMgZGVzaWdud2FyZSBQQ0llIGNvbnRyb2xsZXIuIEFkZA0KPiA+IFNQRUFyMTN4eCBQQ0llIGRy
aXZlciBiYXNlZCBvbiBkZXNpZ253YXJlIGNvbnRyb2xsZXIgZHJpdmVyLg0KPiA+DQo+ID4gU1BF
QXIxMzEwIGhhcyAzIFBDSWUgcG9ydHMgYW5kIFNQRUFyMTM0MCBoYXMgMSwgd2hpY2ggYXJlIG11
bHRpcGxleGVkDQo+ID4gd2l0aCBhaGNpL3NhdGEgcGlucy4gQnkgZGVmYXVsdCBldmFsdWF0aW9u
IGJvYXJkIG9mIGJvdGggY29udHJvbGxlcg0KPiA+IHdvcmtzIGZvciBhaGNpIG1vZGUuDQo+ID4g
VG8gdXNlIHRoZXNlIHBhdGNoZXMgb24gU1BFQXIxMzQwLzEzMTAgZXZhbHVhdGlvbiBib2FyZCwg
ZG8gdGhlDQo+ID4gbmVjZXNzYXJ5IG1vZGlmaWNhdGlvbnMgb24gYm9hcmQgYW5kIGVuYWJsZSAo
b2theSkgcGNpZSBhbmQgbWlwaHkgZnJvbQ0KPiA+IHJlc3BlY3RpdmUgZXZiIGR0c2kgZmlsZS4N
Cj4gPg0KPiA+IFNpZ25lZC1vZmYtYnk6IFByYXR5dXNoIEFuYW5kIDxwcmF0eXVzaC5hbmFuZEBz
dC5jb20+DQo+ID4gU2lnbmVkLW9mZi1ieTogTW9oaXQgS3VtYXIgPG1vaGl0Lmt1bWFyQHN0LmNv
bT4NCj4gPiBDYzogSmluZ29vIEhhbiA8amcxLmhhbkBzYW1zdW5nLmNvbT4NCj4gDQo+IEZvciAn
ZHJpdmVycy9wY2kvaG9zdC9wY2llLXNwZWFyMTN4eC5jJywNCj4gDQo+IFJldmlld2VkLWJ5OiBK
aW5nb28gSGFuIDxqZzEuaGFuQHNhbXN1bmcuY29tPg0KDQotIFRoYW5rcyBmb3IgdGhlIHJldmll
dy4uDQoNClJlZ2FyZHMNCk1vaGl0DQoNCj4gDQo+IEJlc3QgcmVnYXJkcywNCj4gSmluZ29vIEhh
bg0KPiANCj4gPiBDYzogQXJuZCBCZXJnbWFubiA8YXJuZEBhcm5kYi5kZT4NCj4gPiBDYzogVmly
ZXNoIEt1bWFyIDx2aXJlc2gubGludXhAZ21haWwuY29tPg0KPiA+IENjOiBzcGVhci1kZXZlbEBs
aXN0LnN0LmNvbQ0KPiA+IENjOiBsaW51eC1wY2lAdmdlci5rZXJuZWwub3JnDQo+ID4gLS0tDQo+
ID4gIGFyY2gvYXJtL2Jvb3QvZHRzL3NwZWFyMTMxMC5kdHNpICB8ICAgIDYgKw0KPiA+ICBhcmNo
L2FybS9ib290L2R0cy9zcGVhcjEzNDAuZHRzaSAgfCAgICAyICsNCj4gPiAgYXJjaC9hcm0vYm9v
dC9kdHMvc3BlYXIxM3h4LmR0c2kgIHwgICAgNCArLQ0KPiA+ICBhcmNoL2FybS9tYWNoLXNwZWFy
L0tjb25maWcgICAgICAgfCAgICAxICsNCj4gPiAgZHJpdmVycy9wY2kvaG9zdC9LY29uZmlnICAg
ICAgICAgIHwgICAgOCArDQo+ID4gIGRyaXZlcnMvcGNpL2hvc3QvTWFrZWZpbGUgICAgICAgICB8
ICAgIDEgKw0KPiA+ICBkcml2ZXJzL3BjaS9ob3N0L3BjaWUtc3BlYXIxM3h4LmMgfCAgNDE0DQo+
ID4gKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKw0KPiA+ICA3IGZpbGVzIGNo
YW5nZWQsIDQzNCBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKSAgY3JlYXRlIG1vZGUNCj4g
PiAxMDA2NDQgZHJpdmVycy9wY2kvaG9zdC9wY2llLXNwZWFyMTN4eC5jDQo+IA0KDQo=

RE: [PATCH V7 00/10] PCI: Add SPEAr13xx PCie support

[Mohit KUMAR DCG]

SGVsbG8gQXJuZCwNCg0KPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBCam9y
biBIZWxnYWFzIFttYWlsdG86YmhlbGdhYXNAZ29vZ2xlLmNvbV0NCj4gU2VudDogRnJpZGF5LCBN
YXJjaCAyOCwgMjAxNCA5OjU2IFBNDQo+IFRvOiBNYXJrIE5pY2hvbHNvbg0KPiBDYzogTW9oaXQg
S1VNQVIgRENHOyBBcm5kIEJlcmdtYW5uIChhcm5kQGFybmRiLmRlKTsgQmFydGxvbWllag0KPiBa
b2xuaWVya2lld2ljeg0KPiBTdWJqZWN0OiBSZTogW1BBVENIIFY3IDAwLzEwXSBQQ0k6IEFkZCBT
UEVBcjEzeHggUENpZSBzdXBwb3J0DQo+IA0KPiBOb3QgZnJvbSBtZS4gIEl0IHNob3VsZCBiZSBp
biBwYXRjaHdvcmsNCj4gKGh0dHA6Ly9wYXRjaHdvcmsub3psYWJzLm9yZy9wcm9qZWN0L2xpbnV4
LXBjaS9saXN0LyksIHdoZXJlIHlvdSBjYW4NCj4gZG93bmxvYWQgcGF0Y2hlcyBhbmQgYXBwbHkg
bWFudWFsbHkuDQo+IA0KPiBJZiBpdCdzICpub3QqIGluIHBhdGNod29yaywgaXQgbWVhbnMgSSBk
aXNjYXJkZWQgaXQgZm9yIHNvbWUgcmVhc29uDQo+IChzdXBlcnNlZGVkLCBjaGFuZ2VzIHJlcXVl
c3RlZCwgaXQgd2Fzbid0IHNlbnQgdG8gbGludXgtcGNpLCBldGMuLCBhbmQgeW91DQo+IHNob3Vs
ZCByZXNlbmQgaXQgc28gSSdsbCByZW1lbWJlciB0byBsb29rIGF0IGl0Lg0KPiANCi0gWWVzLCBJ
IGNhbiBmaW5kIFBDSWUgc3BlY2lmaWMgcGF0Y2gjOCwxMCBoZXJlLiBJIHRoaW5rIHJlc3Qgb2Yg
dGhlIA0KcGF0Y2hlcyBzaG91bGQgYmUgY29taW5nIHRocm91Z2ggeW91ciB0cmVlLg0KDQpSZWdh
cmRzDQpNb2hpdA0KDQo+IE9uIEZyaSwgTWFyIDI4LCAyMDE0IGF0IDEwOjIxIEFNLCBNYXJrIE5p
Y2hvbHNvbiA8bWFya0BuaWNob2xuZXQuY29tPg0KPiB3cm90ZToNCj4gPiBHcmVhdCEgIEluIHRo
ZSBtZWFuIHRpbWUsIGlzIHRoZXJlIGEgcGxhY2UgdG8gZG93bmxvYWQgdGhlIHBhdGNoc2V0Pw0K
PiA+DQo+ID4gVGhhbmtzIQ0KPiA+IH5NYXJrDQo+ID4NCj4gPg0KPiA+DQo+ID4gT24gRnJpLCBN
YXIgMjgsIDIwMTQgYXQgNzo1MyBBTSwgQmpvcm4gSGVsZ2FhcyA8YmhlbGdhYXNAZ29vZ2xlLmNv
bT4NCj4gd3JvdGU6DQo+ID4+DQo+ID4+IE9uIFRodSwgTWFyIDI3LCAyMDE0IGF0IDEwOjM3IFBN
LCBNb2hpdCBLVU1BUiBEQ0cNCj4gPj4gPE1vaGl0LktVTUFSQHN0LmNvbT4NCj4gPj4gd3JvdGU6
DQo+ID4+ID4gR2VudGxlIFJlbWluZGVyISENCj4gPj4gPg0KPiA+PiA+IEhlbGxvIEJqb3JuLA0K
PiA+PiA+DQo+ID4+ID4gSSBhbSBnZXR0aW5nIG11bHRpcGxlIHF1ZXJpZXMgb24gdGhlIGF2YWls
YWJpbGl0eSBvZiB0aGVzZSBwYXRjaGVzKENDKS4NCj4gPj4gPiBDb3VsZCB5b3UgcGxzIHBpY2sg
dXAgdGhpcyBzZXJpZXMgYXQgbGVhc3QgZm9yIHlvdXIgdHJlZS4NCj4gPj4NCj4gPj4gSSdsbCBz
dGFydCBtZXJnaW5nIHRoaW5ncyBmb3IgdjMuMTYgbmV4dCB3ZWVrIGFmdGVyIHYzLjE0IGlzIHJl
bGVhc2VkLg0KPiA+PiAgRG9uJ3Qgd29ycnksIGl0J3Mgbm90IGZvcmdvdHRlbiA6KQ0KPiA+Pg0K
PiA+PiBCam9ybg0KPiA+Pg0KPiA+PiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+
PiA+PiBGcm9tOiBNb2hpdCBLVU1BUiBEQ0cNCj4gPj4gPj4gU2VudDogRnJpZGF5LCBGZWJydWFy
eSAyOCwgMjAxNCA1OjI1IFBNDQo+ID4+ID4+IFRvOiBhcm5kQGFybmRiLmRlDQo+ID4+ID4+IENj
OiBNb2hpdCBLVU1BUiBEQ0cNCj4gPj4gPj4gU3ViamVjdDogW1BBVENIIFY3IDAwLzEwXSBQQ0k6
IEFkZCBTUEVBcjEzeHggUENpZSBzdXBwb3J0DQo+ID4+ID4+DQo+ID4+ID4+IFBhdGNoIyAxIGFu
ZCAyOiBJbXByb3ZlbWVudCBhbmQgZml4ZXMgZm9yIFNQRUFyMTN4eCBzdXBwb3J0Lg0KPiA+PiA+
PiBQYXRjaCMgMyw0IGFuZCA2OiBBZGQgRFQgYmluZGluZ3MgZm9yIHNwZWFyMTMxMC80MC1taXBo
eSwgbWlzYyBhbmQNCj4gPj4gPj4gcGNpZSBub2RlIFBhdGNoIyA1OiBBZGQgc3BlYXIxMzEwLzQw
LW1pcGh5IGRyaXZlciBhbmQgc3VwcG9ydCBmb3INCj4gPj4gPj4gc3BlYXIxMzEwLzQwDQo+ID4+
ID4+IG1pcGh5IHdyYXBwZXIuDQo+ID4+ID4+IFBhdGNoIyA3LTk6IEFkZCBTUEVBcjEzeHggUENJ
ZSBkcml2ZXIgYW5kIGR0IHN1cHBvcnQuDQo+ID4+ID4+DQo+ID4+ID4+IFRoZXNlIHBhdGhlcyBh
cmUgdGVzdGVkIHdpdGggbGludXgtMy4xNC1yYzEgd2l0aCBmb2xsb3dpbmcgcGF0Y2gNCj4gPj4g
Pj4gb24gdGhlIHRvcCBvZg0KPiA+PiA+PiBpdDoNCj4gPj4gPj4gQXV0aG9yOiBCYWxhamkgVCBL
IDxiYWxhaml0a0B0aS5jb20+DQo+ID4+ID4+IERhdGU6ICAgTW9uIEphbiAyMCAxNjo0MToyNyAy
MDE0ICswMjAwDQo+ID4+ID4+DQo+ID4+ID4+ICAgICBhdGE6IGFoY2lfcGxhdGZvcm06IE1hbmFn
ZSBTQVRBIFBIWQ0KPiA+PiA+Pg0KPiA+PiA+PiBUZXN0ZWQgd2l0aCBTUEVBcjEzMTAgZXZhbHVh
dGlvbiBib2FyZDoNCj4gPj4gPj4gICAgICAgLSBJTlRFTCBQUk8gMTAwLzEwMCBFUCBjYXJkDQo+
ID4+ID4+ICAgICAgIC0gVVNCIHhoY2kgZ2VuMiBjYXJkDQo+ID4+ID4+ICAgICAgIC0gQWJvdmUg
Y2FyZHMgY29ubmVjdGVkIHRocm91Z2ggTGVDUk9ZIFBUQyBzd2l0Y2gNCj4gPj4gPj4NCj4gPj4g
Pj4gTW9kaWZpY2F0aW9ucyBmb3IgU0FUQSBhcmUgdGVzdGVkIHdpdGggU1BFQXIxMzQwLWV2YiBi
b2FyZA0KPiA+PiA+Pg0KPiA+PiA+PiBDaGFuZ2VzIHNpbmNlIHY2Og0KPiA+PiA+PiAtIFNwbGl0
IG1pcGh5IGRyaXZlciBmb3IgU1BFQXIxMzEwIGFuZCBTUEVBcjEzNDANCj4gPj4gPj4gLSBTb21l
IGNsZWFudXAgYW5kIGluY29ycG9yYXRlZCBvdGhlciBtaW5vciBjb21tZW50cyBDaGFuZ2VzDQo+
IHNpbmNlIHY1Og0KPiA+PiA+PiAtIFNwbGl0IERUIGJpbmRpbmdzIGZvciBtaXNjLCBtaXBoeS00
MGxwIGFuZCBwY2llIG5vZGUgaW50bw0KPiA+PiA+PiBzZXBlYXJ0ZSBwYXRjaGVzDQo+ID4+ID4+
IC0gTWVyZ2UgY29uZmlnIG9wdGlvbnMgUENJRV9TUEVBUjEzWFggYW5kIFBDSV9NU0kgaW50byBk
ZWZjb25maWcNCj4gPj4gPj4gcGF0Y2gNCj4gPj4gPj4gLSBJbmNvcnBvcmF0ZWQgb3RoZXIgbWlu
b3IgY29tbWVudHMgQ2hhbmdlcyBzaW5jZSB2NDoNCj4gPj4gPj4gLSBVc2VzIHBlciBkZXZpY2Ug
ZnVuY3Rpb24gcG9pbnRlcnMgcGFzc2VkIGZyb20gLmRhdGEgZmllbGQgdG8NCj4gPj4gPj4gICB0
aGUgb2ZfZGV2aWNlX2lkIGluc3RlYWQgb2Ygb2ZfZGV2aWNlX2lzX2NvbXBhdGlibGUuDQo+ID4+
ID4+IC0gSW5jb3Jwb3JhdGVkIG90aGVyIG1pbm9yIGNvbW1lbnRzIGZyb20gdjQNCj4gPj4gPj4N
Cj4gPj4gPj4gQ2hhbmdlcyBzaW5jZSB2MzoNCj4gPj4gPj4gLSBQaHkgZHJpdmVyIHJlbmFtZWQg
dG8gcGh5LW1pcGh5NDBscA0KPiA+PiA+PiAtIGFoY2kgcGh5IGhvb2sgcGF0Y2ggdXNlZCBhcyBz
dWdnZXN0ZWQgYnkgQXJuZA0KPiA+PiA+PiAtIEluY29ycG9yYXRlZCBvdGhlciBtaW5vciBjb21t
ZW50cyBmcm9tIHYzDQo+ID4+ID4+DQo+ID4+ID4+IENoYW5nZXMgc2luY2UgdjI6DQo+ID4+ID4+
IC0gSW5jb3Jwb3JhdGVkIGNvbW1lbnRzIHRvIG1vdmUgU1BFQXIxM3h4IFBDSWUgYW5kIFNBVEEg
cGh5DQo+ID4+ID4+IHNwZWNpZmljIHJvdXRpbmVzIHRvDQo+ID4+ID4+ICAgdGhlIHBoeSBmcmFt
ZXdvcmsNCj4gPj4gPj4gLSBNb2RpZnkgYWhjaSBkcml2ZXIgdG8gaW5jbHVkZSBwaHkgaG9va3MN
Cj4gPj4gPj4gLSBwaHktY29yZSBkcml2ZXIgbW9kaWZpY2F0aW9ucyBmb3Igc3Vic3lzX2luaXRj
YWxsKCkNCj4gPj4gPj4NCj4gPj4gPj4gQ2hhbmdlcyBzaW5jZSB2MToNCj4gPj4gPj4gLSBGZXcg
cGF0Y2hlcyBvZiB0aGUgc2VyaWVzIGFyZSBhbHJlYWR5IGFjY2VwdGVkIGFuZCBhcHBsaWVkIHRv
DQo+ID4+ID4+IG1haW5saW5lIGUuZy4NCj4gPj4gPj4gIHBjaWUgZGVzaWdud2FyZSBkcml2ZXIg
aW1wcm92ZW1lbnRzLGZpeGVzIGZvciBJTyB0cmFuc2xhdGlvbiBidWcsDQo+ID4+ID4+IFBDSWUg
ZHcgZHJpdmVyIG1haW50YWluZXIuIFNvIGRyb3BwZWQgdGhlc2UgZnJvbSB2Mi4NCj4gPj4gPj4g
LSBJbmNvcnBvcmF0ZWQgY29tbWVudCB0byBtb3ZlIHRoZSBjb21tb24vcmVzZXQgUENJZSBjb2Rl
IHRvIHRoZQ0KPiA+PiA+PiBzZXBlcmF0ZSBkcml2ZXINCj4gPj4gPj4gLSBQQ0llIGFuZCBTQVRB
IHNoYXJlIGNvbW1vbiBQSFkgY29uZmlndXJhdGlvbiByZWdpc3RlcnMsIHNvIG1vdmUNCj4gPj4g
Pj4gU0FUQSBwbGF0Zm9ybSBjb2RlIHRvIHRoZSBzeXN0ZW0gY29uZmlnIGRyaXZlciBGb3VydGgg
cGF0Y2ggaXMNCj4gPj4gPj4gaW1wcm92ZXMgcGNpZSBkZXNpZ253YXJlIGRyaXZlciBhbmQgZml4
ZXMgdGhlIElPIHRyYW5zbGF0aW9uIGJ1Zy4NCj4gPj4gPj4gSU8gdHJhbnNsYXRpb24gYnVnIGZp
eCBsZWFkcyB0byB0aGUgd29ya2luZyBvZiBQQ0llIEVQIGRldmljZXMNCj4gPj4gPj4gY29ubmVj
dGVkIHRvIFJDIHRocm91Z2ggc3dpdGNoLg0KPiA+PiA+Pg0KPiA+PiA+PiBNb2hpdCBLdW1hciAo
Mik6DQo+ID4+ID4+ICAgU1BFQXIxM3h4OiBkZWZjb25maWc6IFVwZGF0ZQ0KPiA+PiA+PiAgIE1B
SU5UQUlORVJTOiBBZGQgU1QgU1BFQXIxM3h4IFBDSWUgZHJpdmVyIG1haW50YWluZXINCj4gPj4g
Pj4NCj4gPj4gPj4gUHJhdHl1c2ggQW5hbmQgKDgpOg0KPiA+PiA+PiAgIGNsazogU1BFQXIxM1hY
OiBGaXggcGNpZSBjbG9jayBuYW1lDQo+ID4+ID4+ICAgU1BFQXIxM1hYOiBGaXggc3RhdGljIG1h
cHBpbmcgdGFibGUNCj4gPj4gPj4gICBwaHk6IFNQRUFyMTMxMC80MC1taXBoeTogQWRkIGJpbmRp
bmcgaW5mb3JtYXRpb24NCj4gPj4gPj4gICBTUEVBcjogbWlzYzogQWRkIGJpbmRpbmcgaW5mb3Jt
YXRpb24NCj4gPj4gPj4gICBwaHk6IFNQRUFyMTMxMC80MC1taXBoeTogQWRkIHBoeSBkcml2ZXIg
Zm9yIFBDSWUgYW5kIFNBVEENCj4gPj4gPj4gICBTUEVBcjEzWFg6IEFkZCBiaW5kaW5nIGluZm9y
bWF0aW9uIGZvciBQQ0llIGNvbnRyb2xsZXINCj4gPj4gPj4gICBTUEVBcjEzWFg6IGR0czogQWRk
IFBDSWUgbm9kZSBpbmZvcm1hdGlvbg0KPiA+PiA+PiAgIHBjaWU6IFNQRUFyMTN4eDogQWRkIGRl
c2lnbndhcmUgd3JhcHBlciBzdXBwb3J0DQo+ID4+ID4+DQo+ID4+ID4+ICAuLi4vZGV2aWNldHJl
ZS9iaW5kaW5ncy9hcm0vc3BlYXItbWlzYy50eHQgICAgICAgICB8ICAgIDkgKw0KPiA+PiA+PiAg
Li4uL2RldmljZXRyZWUvYmluZGluZ3MvcGNpL3NwZWFyMTN4eC1wY2llLnR4dCAgICAgfCAgIDE0
ICsNCj4gPj4gPj4gIC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL3BoeS9zdC1zcGVhcjEzMTAtbWlw
aHkudHh0IHwgICAxMiArDQo+ID4+ID4+ICAuLi4vZGV2aWNldHJlZS9iaW5kaW5ncy9waHkvc3Qt
c3BlYXIxMzQwLW1pcGh5LnR4dCB8ICAgMTEgKw0KPiA+PiA+PiAgTUFJTlRBSU5FUlMgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgICA2ICsNCj4gPj4gPj4gIGFyY2gv
YXJtL2Jvb3QvZHRzL3NwZWFyMTMxMC1ldmIuZHRzICAgICAgICAgICAgICAgIHwgICAgNCArDQo+
ID4+ID4+ICBhcmNoL2FybS9ib290L2R0cy9zcGVhcjEzMTAuZHRzaSAgICAgICAgICAgICAgICAg
ICB8ICAgOTMgKysrKystDQo+ID4+ID4+ICBhcmNoL2FybS9ib290L2R0cy9zcGVhcjEzNDAtZXZi
LmR0cyAgICAgICAgICAgICAgICB8ICAgIDQgKw0KPiA+PiA+PiAgYXJjaC9hcm0vYm9vdC9kdHMv
c3BlYXIxMzQwLmR0c2kgICAgICAgICAgICAgICAgICAgfCAgIDMwICsrLQ0KPiA+PiA+PiAgYXJj
aC9hcm0vYm9vdC9kdHMvc3BlYXIxM3h4LmR0c2kgICAgICAgICAgICAgICAgICAgfCAgICA5ICst
DQo+ID4+ID4+ICBhcmNoL2FybS9jb25maWdzL3NwZWFyMTN4eF9kZWZjb25maWcgICAgICAgICAg
ICAgICB8ICAgMTYgKw0KPiA+PiA+PiAgYXJjaC9hcm0vbWFjaC1zcGVhci9LY29uZmlnICAgICAg
ICAgICAgICAgICAgICAgICAgfCAgICA0ICsNCj4gPj4gPj4gIGFyY2gvYXJtL21hY2gtc3BlYXIv
aW5jbHVkZS9tYWNoL3NwZWFyLmggICAgICAgICAgIHwgICAgNCArLQ0KPiA+PiA+PiAgYXJjaC9h
cm0vbWFjaC1zcGVhci9zcGVhcjEzNDAuYyAgICAgICAgICAgICAgICAgICAgfCAgMTI3ICstLS0t
LS0NCj4gPj4gPj4gIGFyY2gvYXJtL21hY2gtc3BlYXIvc3BlYXIxM3h4LmMgICAgICAgICAgICAg
ICAgICAgIHwgICAgMiArLQ0KPiA+PiA+PiAgZHJpdmVycy9jbGsvc3BlYXIvc3BlYXIxMzEwX2Ns
b2NrLmMgICAgICAgICAgICAgICAgfCAgICA2ICstDQo+ID4+ID4+ICBkcml2ZXJzL2Nsay9zcGVh
ci9zcGVhcjEzNDBfY2xvY2suYyAgICAgICAgICAgICAgICB8ICAgIDIgKy0NCj4gPj4gPj4gIGRy
aXZlcnMvcGNpL2hvc3QvS2NvbmZpZyAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAgOCAr
DQo+ID4+ID4+ICBkcml2ZXJzL3BjaS9ob3N0L01ha2VmaWxlICAgICAgICAgICAgICAgICAgICAg
ICAgICB8ICAgIDEgKw0KPiA+PiA+PiAgZHJpdmVycy9wY2kvaG9zdC9wY2llLXNwZWFyMTN4eC5j
ICAgICAgICAgICAgICAgICAgfCAgNDE0DQo+ID4+ID4+ICsrKysrKysrKysrKysrKysrKysrDQo+
ID4+ID4+ICBkcml2ZXJzL3BoeS9LY29uZmlnICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICB8ICAgMTIgKw0KPiA+PiA+PiAgZHJpdmVycy9waHkvTWFrZWZpbGUgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgfCAgICAyICsNCj4gPj4gPj4gIGRyaXZlcnMvcGh5L3BoeS1zcGVhcjEz
MTAtbWlwaHkuYyAgICAgICAgICAgICAgICAgIHwgIDI3NA0KPiA+PiA+PiArKysrKysrKysrKysr
DQo+ID4+ID4+ICBkcml2ZXJzL3BoeS9waHktc3BlYXIxMzQwLW1pcGh5LmMgICAgICAgICAgICAg
ICAgICB8ICAzMDANCj4gPj4gPj4gKysrKysrKysrKysrKysNCj4gPj4gPj4gIDI0IGZpbGVzIGNo
YW5nZWQsIDEyMjUgaW5zZXJ0aW9ucygrKSwgMTM5IGRlbGV0aW9ucygtKSAgY3JlYXRlDQo+ID4+
ID4+IG1vZGUNCj4gPj4gPj4gMTAwNjQ0DQo+ID4+ID4+IERvY3VtZW50YXRpb24vZGV2aWNldHJl
ZS9iaW5kaW5ncy9hcm0vc3BlYXItbWlzYy50eHQNCj4gPj4gPj4gIGNyZWF0ZSBtb2RlIDEwMDY0
NA0KPiA+PiA+PiBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGNpL3NwZWFyMTN4
eC0NCj4gPj4gPj4gcGNpZS50eHQNCj4gPj4gPj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBEb2N1bWVu
dGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGh5L3N0LQ0KPiA+PiA+PiBzcGVhcjEzMTAtbWlw
aHkudHh0DQo+ID4+ID4+ICBjcmVhdGUgbW9kZSAxMDA2NDQgRG9jdW1lbnRhdGlvbi9kZXZpY2V0
cmVlL2JpbmRpbmdzL3BoeS9zdC0NCj4gPj4gPj4gc3BlYXIxMzQwLW1pcGh5LnR4dA0KPiA+PiA+
PiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvcGNpL2hvc3QvcGNpZS1zcGVhcjEzeHguYyAg
Y3JlYXRlIG1vZGUNCj4gPj4gPj4gMTAwNjQ0DQo+ID4+ID4+IGRyaXZlcnMvcGh5L3BoeS1zcGVh
cjEzMTAtbWlwaHkuYyAgY3JlYXRlIG1vZGUgMTAwNjQ0DQo+ID4+ID4+IGRyaXZlcnMvcGh5L3Bo
eS0gc3BlYXIxMzQwLW1pcGh5LmMNCj4gPj4gPg0KPiA+DQo+ID4NCg==

Re: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support

[Bjorn Helgaas]

On Fri, Feb 28, 2014 at 05:25:01PM +0530, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
> SPEAr13xx PCIe driver based on designware controller driver.
> 
> SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
> with ahci/sata pins. By default evaluation board of both controller
> works for ahci mode.
> To use these patches on SPEAr1340/1310 evaluation board, do the
> necessary modifications on board and enable (okay) pcie and miphy
> from respective evb dtsi file.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
>  arch/arm/boot/dts/spear1310.dtsi  |    6 +
>  arch/arm/boot/dts/spear1340.dtsi  |    2 +
>  arch/arm/boot/dts/spear13xx.dtsi  |    4 +-
>  arch/arm/mach-spear/Kconfig       |    1 +
>  drivers/pci/host/Kconfig          |    8 +
>  drivers/pci/host/Makefile         |    1 +
>  drivers/pci/host/pcie-spear13xx.c |  414 +++++++++++++++++++++++++++++++++++++

This doesn't apply cleanly to my tree (currently at 4a4389abdd98),
apparently because I don't have some of the ARM DTS stuff.  If you want to
split this into a PCI-specific part and an arch/arm part, I can apply the
PCI part.  Or you can apply the whole thing via whatever ARM tree makes
sense.

I do have a couple minor comments below.  With those addressed, here's my
ACK so you can merge it via another tree if that makes the most sense:

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 47d46c6..8697dd1 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -33,4 +33,12 @@ config PCI_RCAR_GEN2
>  	  There are 3 internal PCI controllers available with a single
>  	  built-in EHCI/OHCI host controller present on each one.
>  
> +config PCIE_SPEAR13XX
> +	tristate "STMicroelectronics SPEAr PCIe controller"
> +	depends on ARCH_SPEAR13XX
> +	select PCIEPORTBUS
> +	select PCIE_DW
> +	help
> +	  Say Y here if you want PCIe support on SPEAr13XX SoCs.
> +
>  endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 13fb333..42a491d 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
>  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
> new file mode 100644
> index 0000000..c70d526
> --- /dev/null
> +++ b/drivers/pci/host/pcie-spear13xx.c
> @@ -0,0 +1,414 @@
> +/*
> + * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
> + *
> + * SPEAr13xx PCIe Glue Layer Source Code
> + *
> + * Copyright (C) 2010-2014 ST Microelectronics
> + * Pratyush Anand <pratyush.anand@st.com>
> + * Mohit Kumar <mohit.kumar@st.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pci.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +
> +#include "pcie-designware.h"
> +
> +struct spear13xx_pcie {
> +	void __iomem		*app_base;
> +	struct phy		*phy;
> +	struct clk		*clk;
> +	struct pcie_port	pp;
> +	bool			is_gen1;
> +};
> +
> +struct pcie_app_reg {
> +	u32	app_ctrl_0;		/*cr0*/
> +	u32	app_ctrl_1;		/*cr1*/
> +	u32	app_status_0;		/*cr2*/
> +	u32	app_status_1;		/*cr3*/
> +	u32	msg_status;		/*cr4*/
> +	u32	msg_payload;		/*cr5*/
> +	u32	int_sts;		/*cr6*/
> +	u32	int_clr;		/*cr7*/
> +	u32	int_mask;		/*cr8*/
> +	u32	mst_bmisc;		/*cr9*/
> +	u32	phy_ctrl;		/*cr10*/
> +	u32	phy_status;		/*cr11*/
> +	u32	cxpl_debug_info_0;	/*cr12*/
> +	u32	cxpl_debug_info_1;	/*cr13*/
> +	u32	ven_msg_ctrl_0;		/*cr14*/
> +	u32	ven_msg_ctrl_1;		/*cr15*/
> +	u32	ven_msg_data_0;		/*cr16*/
> +	u32	ven_msg_data_1;		/*cr17*/
> +	u32	ven_msi_0;		/*cr18*/
> +	u32	ven_msi_1;		/*cr19*/
> +	u32	mst_rmisc;		/*cr 20*/

Usually people put a space after "/*" and before "*/" (this applies other
places below, too).  But at least make the cr20 comment spacing here
consistent with the other ones above.

> +};
> +
> +/*CR0 ID*/
> +#define RX_LANE_FLIP_EN_ID			0
> +#define TX_LANE_FLIP_EN_ID			1
> +#define SYS_AUX_PWR_DET_ID			2
> +#define APP_LTSSM_ENABLE_ID			3
> +#define SYS_ATTEN_BUTTON_PRESSED_ID		4
> +#define SYS_MRL_SENSOR_STATE_ID			5
> +#define SYS_PWR_FAULT_DET_ID			6
> +#define SYS_MRL_SENSOR_CHGED_ID			7
> +#define SYS_PRE_DET_CHGED_ID			8
> +#define SYS_CMD_CPLED_INT_ID			9
> +#define APP_INIT_RST_0_ID			11
> +#define APP_REQ_ENTR_L1_ID			12
> +#define APP_READY_ENTR_L23_ID			13
> +#define APP_REQ_EXIT_L1_ID			14
> +#define DEVICE_TYPE_EP				(0 << 25)
> +#define DEVICE_TYPE_LEP				(1 << 25)
> +#define DEVICE_TYPE_RC				(4 << 25)
> +#define SYS_INT_ID				29
> +#define MISCTRL_EN_ID				30
> +#define REG_TRANSLATION_ENABLE			31

Many of these symbols are defined but never used.  Personally, I would just
define the things you use, since they've presumably gotten at least some
testing.  Then the list is a clue to the reader about what features the
driver supports, and you can add others when you add more features.  I
think they're more likely to get reviewed and tested then.  But not a big
deal either way.

> +/*CR1 ID*/
> +#define APPS_PM_XMT_TURNOFF_ID			2
> +#define APPS_PM_XMT_PME_ID			5
> +
> +/*CR3 ID*/
> +#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
> +#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
> +#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
> +#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
> +#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
> +#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
> +#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
> +#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
> +#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
> +#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
> +#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
> +#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
> +#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
> +#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
> +#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
> +#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
> +#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
> +#define XMLH_LTSSM_STATE_L0			0x11
> +#define XMLH_LTSSM_STATE_L0S			0x12
> +#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
> +#define XMLH_LTSSM_STATE_L1_IDLE		0x14
> +#define XMLH_LTSSM_STATE_L2_IDLE		0x15
> +#define XMLH_LTSSM_STATE_L2_WAKE		0x16
> +#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
> +#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
> +#define XMLH_LTSSM_STATE_DISABLED		0x19
> +#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
> +#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
> +#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
> +#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
> +#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
> +#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
> +#define XMLH_LTSSM_STATE_MASK			0x3F
> +#define XMLH_LINK_UP				(1 << 6)
> +
> +/*CR4 ID*/
> +#define CFG_MSI_EN_ID				18
> +
> +/*CR6*/
> +#define INTA_CTRL_INT				(1 << 7)
> +#define INTB_CTRL_INT				(1 << 8)
> +#define INTC_CTRL_INT				(1 << 9)
> +#define INTD_CTRL_INT				(1 << 10)
> +#define MSI_CTRL_INT				(1 << 26)
> +
> +/*CR19 ID*/
> +#define VEN_MSI_REQ_ID				11
> +#define VEN_MSI_FUN_NUM_ID			8
> +#define VEN_MSI_TC_ID				5
> +#define VEN_MSI_VECTOR_ID			0
> +#define VEN_MSI_REQ_EN		((u32)0x1 << VEN_MSI_REQ_ID)
> +#define VEN_MSI_FUN_NUM_MASK	((u32)0x7 << VEN_MSI_FUN_NUM_ID)
> +#define VEN_MSI_TC_MASK		((u32)0x7 << VEN_MSI_TC_ID)
> +#define VEN_MSI_VECTOR_MASK	((u32)0x1F << VEN_MSI_VECTOR_ID)
> +
> +#define PCI_CAP_ID_EXP_OFFSET			0x70
> +
> +#define to_spear13xx_pcie(x)	container_of(x, struct spear13xx_pcie, pp)
> +
> +static int spear13xx_pcie_establish_link(struct pcie_port *pp)
> +{
> +	u32 val;
> +	int count = 0;
> +	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> +	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> +	u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
> +
> +	if (dw_pcie_link_up(pp)) {
> +		dev_err(pp->dev, "Link already up\n");

Most of your messages start with lowercase; it'd be nice to be consistent.

> +		return 0;
> +	}
> +
> +	/* setup root complex */

Superfluous comment.

> +	dw_pcie_setup_rc(pp);
> +
> +	/*
> +	 * this controller support only 128 bytes read size, however its
> +	 * default value in capability register is 512 bytes. So force
> +	 * it to 128 here.
> +	 */
> +	dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
> +	val &= ~PCI_EXP_DEVCTL_READRQ;
> +	dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
> +
> +	/* program vid and did for RC */

Superfluous comment.

> +	dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
> +	dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
> +
> +	/*
> +	 * if is_gen1 is set then handle it, so that some buggy card
> +	 * also works
> +	 */
> +	if (spear13xx_pcie->is_gen1) {
> +		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
> +				&val);
> +		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
> +			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> +			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> +			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> +					PCI_EXP_LNKCAP, 4, val);
> +		}
> +
> +		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
> +				&val);
> +		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
> +			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> +			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> +			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> +					PCI_EXP_LNKCTL2, 4, val);
> +		}
> +	}
> +
> +	/* enable ltssm */
> +	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
> +			| (1 << APP_LTSSM_ENABLE_ID)
> +			| ((u32)1 << REG_TRANSLATION_ENABLE),
> +			&app_reg->app_ctrl_0);
> +
> +	/* check if the link is up or not */
> +	while (!dw_pcie_link_up(pp)) {
> +		mdelay(100);
> +		count++;
> +		if (count == 10) {
> +			dev_err(pp->dev, "Link Fail\n");
> +			return -EINVAL;
> +		}
> +	}
> +	dev_info(pp->dev, "Link up\n");
> +
> +	return 0;
> +}
> +
> +static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
> +{
> +	struct pcie_port *pp = arg;
> +	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> +	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> +	unsigned int status;
> +
> +	status = readl(&app_reg->int_sts);
> +
> +	if (status & MSI_CTRL_INT) {
> +		if (!IS_ENABLED(CONFIG_PCI_MSI))
> +			BUG();
> +		dw_handle_msi_irq(pp);
> +	}
> +
> +	writel(status, &app_reg->int_clr);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
> +{
> +	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> +	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> +
> +	/* Enable MSI interrupt */
> +	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> +		dw_pcie_msi_init(pp);
> +		writel(readl(&app_reg->int_mask) |
> +				MSI_CTRL_INT, &app_reg->int_mask);
> +	}
> +
> +	return;

Superfluous "return".

> +}
> +
> +static int spear13xx_pcie_link_up(struct pcie_port *pp)
> +{
> +	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> +	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> +
> +	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
> +		return 1;
> +
> +	return 0;
> +}
> +
> +static void spear13xx_pcie_host_init(struct pcie_port *pp)
> +{
> +	spear13xx_pcie_establish_link(pp);
> +	spear13xx_pcie_enable_interrupts(pp);
> +}
> +
> +static struct pcie_host_ops spear13xx_pcie_host_ops = {
> +	.link_up = spear13xx_pcie_link_up,
> +	.host_init = spear13xx_pcie_host_init,
> +};
> +
> +static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	pp->irq = platform_get_irq(pdev, 0);
> +	if (!pp->irq) {
> +		dev_err(dev, "failed to get irq\n");
> +		return -ENODEV;
> +	}
> +	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
> +				IRQF_SHARED, "spear1340-pcie", pp);
> +	if (ret) {
> +		dev_err(dev, "failed to request irq\n");

Please include the IRQ number in this message.

> +		return ret;
> +	}
> +
> +	pp->root_bus_nr = -1;
> +	pp->ops = &spear13xx_pcie_host_ops;
> +
> +	spin_lock_init(&pp->conf_lock);
> +	ret = dw_pcie_host_init(pp);
> +	if (ret) {
> +		dev_err(dev, "failed to initialize host\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int __init spear13xx_pcie_probe(struct platform_device *pdev)
> +{
> +	struct spear13xx_pcie *spear13xx_pcie;
> +	struct pcie_port *pp;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = pdev->dev.of_node;
> +	struct resource *dbi_base;
> +	int ret;
> +
> +	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
> +				GFP_KERNEL);
> +	if (!spear13xx_pcie) {
> +		dev_err(dev, "no memory for SPEAr13xx pcie\n");
> +		return -ENOMEM;
> +	}
> +
> +	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> +	if (IS_ERR(spear13xx_pcie->phy)) {
> +		ret = PTR_ERR(spear13xx_pcie->phy);
> +		switch (ret) {
> +		case -EPROBE_DEFER:
> +			dev_info(dev, "probe deferred\n");
> +			return ret;
> +		default:
> +			dev_err(dev, "couldn't get pcie-phy\n");
> +			return ret;
> +		}

This would be slightly simpler (your choice):

	if (ret == -EPROBE_DEFER)
		dev_info(...)
	else
		dev_err(...)
	return ret;

> +	}
> +
> +	phy_init(spear13xx_pcie->phy);
> +
> +	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(spear13xx_pcie->clk)) {
> +		dev_err(dev, "couldn't get clk for pcie\n");
> +		return PTR_ERR(spear13xx_pcie->clk);
> +	}
> +	ret = clk_prepare_enable(spear13xx_pcie->clk);
> +	if (ret) {
> +		dev_err(dev, "couldn't enable clk for pcie\n");
> +		return ret;
> +	}
> +
> +	pp = &spear13xx_pcie->pp;
> +
> +	pp->dev = dev;
> +
> +	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
> +	if (IS_ERR(pp->dbi_base)) {
> +		dev_err(dev, "couldn't remap dbi base\n");

Please include the dbi_base address in the message.

> +		ret = PTR_ERR(pp->dbi_base);
> +		goto fail_clk;
> +	}
> +	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
> +
> +	if (of_property_read_bool(np, "st,pcie-is-gen1"))
> +		spear13xx_pcie->is_gen1 = true;
> +
> +	ret = add_pcie_port(pp, pdev);
> +	if (ret < 0)
> +		goto fail_clk;
> +
> +	platform_set_drvdata(pdev, spear13xx_pcie);
> +	return 0;
> +
> +fail_clk:
> +	clk_disable_unprepare(spear13xx_pcie->clk);
> +
> +	return ret;
> +}
> +
> +static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
> +{
> +	struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
> +
> +	clk_disable_unprepare(spear13xx_pcie->clk);
> +
> +	phy_exit(spear13xx_pcie->phy);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id spear13xx_pcie_of_match[] = {
> +	{ .compatible = "st,spear1340-pcie", },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
> +
> +static struct platform_driver spear13xx_pcie_driver = {
> +	.probe		= spear13xx_pcie_probe,
> +	.remove		= spear13xx_pcie_remove,
> +	.driver = {
> +		.name	= "spear-pcie",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
> +	},
> +};
> +
> +/* SPEAr13xx PCIe driver does not allow module unload */
> +
> +static int __init pcie_init(void)
> +{
> +	return platform_driver_register(&spear13xx_pcie_driver);
> +}
> +module_init(pcie_init);
> +
> +MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
> +MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.7.0.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH V7 10/10] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

[Bjorn Helgaas]

On Fri, Feb 28, 2014 at 05:25:03PM +0530, Mohit Kumar wrote:
> Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
> 
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Acked-by: Jingoo Han <jg1.han@samsung.com>
> Cc: linux-pci@vger.kernel.org

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

Please merge this along with the drivers/pci/host/pcie-spear13xx.c patch.

> ---
>  MAINTAINERS |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b2cf5cf..ebdca89 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6596,6 +6596,12 @@ L:	linux-pci@vger.kernel.org
>  S:	Maintained
>  F:	drivers/pci/host/*designware*
>  
> +PCIE DRIVER FOR ST SPEAR13XX
> +M:	Mohit Kumar <mohit.kumar@st.com>
> +L:	linux-pci@vger.kernel.org
> +S:	Maintained
> +F:	drivers/pci/host/pcie-spear13xx.c
> +
>  PCMCIA SUBSYSTEM
>  P:	Linux PCMCIA Team
>  L:	linux-pcmcia@lists.infradead.org
> -- 
> 1.7.0.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper support

[Mohit KUMAR DCG]

Hello Bjorn,

> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> Sent: Friday, April 04, 2014 10:13 PM
> To: Mohit KUMAR DCG
> Cc: arnd@arndb.de; Pratyush ANAND; Jingoo Han; Viresh Kumar; spear-
> devel; linux-pci@vger.kernel.org
> Subject: Re: [PATCH V7 08/10] pcie: SPEAr13xx: Add designware wrapper
> support
>
> On Fri, Feb 28, 2014 at 05:25:01PM +0530, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
> > SPEAr13xx PCIe driver based on designware controller driver.
> >
> > SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
> > with ahci/sata pins. By default evaluation board of both controller
> > works for ahci mode.
> > To use these patches on SPEAr1340/1310 evaluation board, do the
> > necessary modifications on board and enable (okay) pcie and miphy from
> > respective evb dtsi file.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-pci@vger.kernel.org
> > ---
> >  arch/arm/boot/dts/spear1310.dtsi  |    6 +
> >  arch/arm/boot/dts/spear1340.dtsi  |    2 +
> >  arch/arm/boot/dts/spear13xx.dtsi  |    4 +-
> >  arch/arm/mach-spear/Kconfig       |    1 +
> >  drivers/pci/host/Kconfig          |    8 +
> >  drivers/pci/host/Makefile         |    1 +
> >  drivers/pci/host/pcie-spear13xx.c |  414
> > +++++++++++++++++++++++++++++++++++++
>
> This doesn't apply cleanly to my tree (currently at 4a4389abdd98), apparently
> because I don't have some of the ARM DTS stuff.  If you want to split this into
> a PCI-specific part and an arch/arm part, I can apply the PCI part.  Or you can
> apply the whole thing via whatever ARM tree makes sense.
>

Arnd,
Pls comment if it can be taken care by you if I resend after rebasing it to your tree?

> I do have a couple minor comments below.  With those addressed, here's my
> ACK so you can merge it via another tree if that makes the most sense:
>
- Thanks for your review and comments. I  will incorporate these in my resend patch.

> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>
Thanks
Mohit

> > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index
> > 47d46c6..8697dd1 100644
> > --- a/drivers/pci/host/Kconfig
> > +++ b/drivers/pci/host/Kconfig
> > @@ -33,4 +33,12 @@ config PCI_RCAR_GEN2
> >       There are 3 internal PCI controllers available with a single
> >       built-in EHCI/OHCI host controller present on each one.
> >
> > +config PCIE_SPEAR13XX
> > +   tristate "STMicroelectronics SPEAr PCIe controller"
> > +   depends on ARCH_SPEAR13XX
> > +   select PCIEPORTBUS
> > +   select PCIE_DW
> > +   help
> > +     Say Y here if you want PCIe support on SPEAr13XX SoCs.
> > +
> >  endmenu
> > diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> > index 13fb333..42a491d 100644
> > --- a/drivers/pci/host/Makefile
> > +++ b/drivers/pci/host/Makefile
> > @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> >  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
> >  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
> >  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> > +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> > diff --git a/drivers/pci/host/pcie-spear13xx.c
> > b/drivers/pci/host/pcie-spear13xx.c
> > new file mode 100644
> > index 0000000..c70d526
> > --- /dev/null
> > +++ b/drivers/pci/host/pcie-spear13xx.c
> > @@ -0,0 +1,414 @@
> > +/*
> > + * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
> > + *
> > + * SPEAr13xx PCIe Glue Layer Source Code
> > + *
> > + * Copyright (C) 2010-2014 ST Microelectronics
> > + * Pratyush Anand <pratyush.anand@st.com>
> > + * Mohit Kumar <mohit.kumar@st.com>
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/pci.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +
> > +#include "pcie-designware.h"
> > +
> > +struct spear13xx_pcie {
> > +   void __iomem            *app_base;
> > +   struct phy              *phy;
> > +   struct clk              *clk;
> > +   struct pcie_port        pp;
> > +   bool                    is_gen1;
> > +};
> > +
> > +struct pcie_app_reg {
> > +   u32     app_ctrl_0;             /*cr0*/
> > +   u32     app_ctrl_1;             /*cr1*/
> > +   u32     app_status_0;           /*cr2*/
> > +   u32     app_status_1;           /*cr3*/
> > +   u32     msg_status;             /*cr4*/
> > +   u32     msg_payload;            /*cr5*/
> > +   u32     int_sts;                /*cr6*/
> > +   u32     int_clr;                /*cr7*/
> > +   u32     int_mask;               /*cr8*/
> > +   u32     mst_bmisc;              /*cr9*/
> > +   u32     phy_ctrl;               /*cr10*/
> > +   u32     phy_status;             /*cr11*/
> > +   u32     cxpl_debug_info_0;      /*cr12*/
> > +   u32     cxpl_debug_info_1;      /*cr13*/
> > +   u32     ven_msg_ctrl_0;         /*cr14*/
> > +   u32     ven_msg_ctrl_1;         /*cr15*/
> > +   u32     ven_msg_data_0;         /*cr16*/
> > +   u32     ven_msg_data_1;         /*cr17*/
> > +   u32     ven_msi_0;              /*cr18*/
> > +   u32     ven_msi_1;              /*cr19*/
> > +   u32     mst_rmisc;              /*cr 20*/
>
> Usually people put a space after "/*" and before "*/" (this applies other
> places below, too).  But at least make the cr20 comment spacing here
> consistent with the other ones above.
>
> > +};
> > +
> > +/*CR0 ID*/
> > +#define RX_LANE_FLIP_EN_ID                 0
> > +#define TX_LANE_FLIP_EN_ID                 1
> > +#define SYS_AUX_PWR_DET_ID                 2
> > +#define APP_LTSSM_ENABLE_ID                        3
> > +#define SYS_ATTEN_BUTTON_PRESSED_ID                4
> > +#define SYS_MRL_SENSOR_STATE_ID                    5
> > +#define SYS_PWR_FAULT_DET_ID                       6
> > +#define SYS_MRL_SENSOR_CHGED_ID                    7
> > +#define SYS_PRE_DET_CHGED_ID                       8
> > +#define SYS_CMD_CPLED_INT_ID                       9
> > +#define APP_INIT_RST_0_ID                  11
> > +#define APP_REQ_ENTR_L1_ID                 12
> > +#define APP_READY_ENTR_L23_ID                      13
> > +#define APP_REQ_EXIT_L1_ID                 14
> > +#define DEVICE_TYPE_EP                             (0 << 25)
> > +#define DEVICE_TYPE_LEP                            (1 << 25)
> > +#define DEVICE_TYPE_RC                             (4 << 25)
> > +#define SYS_INT_ID                         29
> > +#define MISCTRL_EN_ID                              30
> > +#define REG_TRANSLATION_ENABLE                     31
>
> Many of these symbols are defined but never used.  Personally, I would just
> define the things you use, since they've presumably gotten at least some
> testing.  Then the list is a clue to the reader about what features the driver
> supports, and you can add others when you add more features.  I think
> they're more likely to get reviewed and tested then.  But not a big deal either
> way.
>
> > +/*CR1 ID*/
> > +#define APPS_PM_XMT_TURNOFF_ID                     2
> > +#define APPS_PM_XMT_PME_ID                 5
> > +
> > +/*CR3 ID*/
> > +#define XMLH_LTSSM_STATE_DETECT_QUIET              0x00
> > +#define XMLH_LTSSM_STATE_DETECT_ACT                0x01
> > +#define XMLH_LTSSM_STATE_POLL_ACTIVE               0x02
> > +#define XMLH_LTSSM_STATE_POLL_COMPLIANCE   0x03
> > +#define XMLH_LTSSM_STATE_POLL_CONFIG               0x04
> > +#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET  0x05
> > +#define XMLH_LTSSM_STATE_DETECT_WAIT               0x06
> > +#define XMLH_LTSSM_STATE_CFG_LINKWD_START  0x07
> > +#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT  0x08
> > +#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT  0x09
> > +#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
> > +#define XMLH_LTSSM_STATE_CFG_COMPLETE              0x0B
> > +#define XMLH_LTSSM_STATE_CFG_IDLE          0x0C
> > +#define XMLH_LTSSM_STATE_RCVRY_LOCK                0x0D
> > +#define XMLH_LTSSM_STATE_RCVRY_SPEED               0x0E
> > +#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG             0x0F
> > +#define XMLH_LTSSM_STATE_RCVRY_IDLE                0x10
> > +#define XMLH_LTSSM_STATE_L0                        0x11
> > +#define XMLH_LTSSM_STATE_L0S                       0x12
> > +#define XMLH_LTSSM_STATE_L123_SEND_EIDLE   0x13
> > +#define XMLH_LTSSM_STATE_L1_IDLE           0x14
> > +#define XMLH_LTSSM_STATE_L2_IDLE           0x15
> > +#define XMLH_LTSSM_STATE_L2_WAKE           0x16
> > +#define XMLH_LTSSM_STATE_DISABLED_ENTRY            0x17
> > +#define XMLH_LTSSM_STATE_DISABLED_IDLE             0x18
> > +#define XMLH_LTSSM_STATE_DISABLED          0x19
> > +#define XMLH_LTSSM_STATE_LPBK_ENTRY                0x1A
> > +#define XMLH_LTSSM_STATE_LPBK_ACTIVE               0x1B
> > +#define XMLH_LTSSM_STATE_LPBK_EXIT         0x1C
> > +#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
> > +#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY   0x1E
> > +#define XMLH_LTSSM_STATE_HOT_RESET         0x1F
> > +#define XMLH_LTSSM_STATE_MASK                      0x3F
> > +#define XMLH_LINK_UP                               (1 << 6)
> > +
> > +/*CR4 ID*/
> > +#define CFG_MSI_EN_ID                              18
> > +
> > +/*CR6*/
> > +#define INTA_CTRL_INT                              (1 << 7)
> > +#define INTB_CTRL_INT                              (1 << 8)
> > +#define INTC_CTRL_INT                              (1 << 9)
> > +#define INTD_CTRL_INT                              (1 << 10)
> > +#define MSI_CTRL_INT                               (1 << 26)
> > +
> > +/*CR19 ID*/
> > +#define VEN_MSI_REQ_ID                             11
> > +#define VEN_MSI_FUN_NUM_ID                 8
> > +#define VEN_MSI_TC_ID                              5
> > +#define VEN_MSI_VECTOR_ID                  0
> > +#define VEN_MSI_REQ_EN             ((u32)0x1 << VEN_MSI_REQ_ID)
> > +#define VEN_MSI_FUN_NUM_MASK       ((u32)0x7 <<
> VEN_MSI_FUN_NUM_ID)
> > +#define VEN_MSI_TC_MASK            ((u32)0x7 <<
> VEN_MSI_TC_ID)
> > +#define VEN_MSI_VECTOR_MASK        ((u32)0x1F << VEN_MSI_VECTOR_ID)
> > +
> > +#define PCI_CAP_ID_EXP_OFFSET                      0x70
> > +
> > +#define to_spear13xx_pcie(x)       container_of(x, struct
> spear13xx_pcie, pp)
> > +
> > +static int spear13xx_pcie_establish_link(struct pcie_port *pp) {
> > +   u32 val;
> > +   int count = 0;
> > +   struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > +   struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > +   u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
> > +
> > +   if (dw_pcie_link_up(pp)) {
> > +           dev_err(pp->dev, "Link already up\n");
>
> Most of your messages start with lowercase; it'd be nice to be consistent.
>
> > +           return 0;
> > +   }
> > +
> > +   /* setup root complex */
>
> Superfluous comment.
>
> > +   dw_pcie_setup_rc(pp);
> > +
> > +   /*
> > +    * this controller support only 128 bytes read size, however its
> > +    * default value in capability register is 512 bytes. So force
> > +    * it to 128 here.
> > +    */
> > +   dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL,
> 4, &val);
> > +   val &= ~PCI_EXP_DEVCTL_READRQ;
> > +   dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL,
> 4,
> > +val);
> > +
> > +   /* program vid and did for RC */
>
> Superfluous comment.
>
> > +   dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
> > +   dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
> > +
> > +   /*
> > +    * if is_gen1 is set then handle it, so that some buggy card
> > +    * also works
> > +    */
> > +   if (spear13xx_pcie->is_gen1) {
> > +           dw_pcie_cfg_read(pp->dbi_base, exp_cap_off +
> PCI_EXP_LNKCAP, 4,
> > +                           &val);
> > +           if ((val & PCI_EXP_LNKCAP_SLS) !=
> PCI_EXP_LNKCAP_SLS_2_5GB) {
> > +                   val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> > +                   val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> > +                   dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> > +                                   PCI_EXP_LNKCAP, 4, val);
> > +           }
> > +
> > +           dw_pcie_cfg_read(pp->dbi_base, exp_cap_off +
> PCI_EXP_LNKCTL2, 4,
> > +                           &val);
> > +           if ((val & PCI_EXP_LNKCAP_SLS) !=
> PCI_EXP_LNKCAP_SLS_2_5GB) {
> > +                   val &= ~((u32)PCI_EXP_LNKCAP_SLS);
> > +                   val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> > +                   dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
> > +                                   PCI_EXP_LNKCTL2, 4, val);
> > +           }
> > +   }
> > +
> > +   /* enable ltssm */
> > +   writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
> > +                   | (1 << APP_LTSSM_ENABLE_ID)
> > +                   | ((u32)1 << REG_TRANSLATION_ENABLE),
> > +                   &app_reg->app_ctrl_0);
> > +
> > +   /* check if the link is up or not */
> > +   while (!dw_pcie_link_up(pp)) {
> > +           mdelay(100);
> > +           count++;
> > +           if (count == 10) {
> > +                   dev_err(pp->dev, "Link Fail\n");
> > +                   return -EINVAL;
> > +           }
> > +   }
> > +   dev_info(pp->dev, "Link up\n");
> > +
> > +   return 0;
> > +}
> > +
> > +static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) {
> > +   struct pcie_port *pp = arg;
> > +   struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > +   struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > +   unsigned int status;
> > +
> > +   status = readl(&app_reg->int_sts);
> > +
> > +   if (status & MSI_CTRL_INT) {
> > +           if (!IS_ENABLED(CONFIG_PCI_MSI))
> > +                   BUG();
> > +           dw_handle_msi_irq(pp);
> > +   }
> > +
> > +   writel(status, &app_reg->int_clr);
> > +
> > +   return IRQ_HANDLED;
> > +}
> > +
> > +static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp) {
> > +   struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > +   struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > +
> > +   /* Enable MSI interrupt */
> > +   if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > +           dw_pcie_msi_init(pp);
> > +           writel(readl(&app_reg->int_mask) |
> > +                           MSI_CTRL_INT, &app_reg->int_mask);
> > +   }
> > +
> > +   return;
>
> Superfluous "return".
>
> > +}
> > +
> > +static int spear13xx_pcie_link_up(struct pcie_port *pp) {
> > +   struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
> > +   struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
> > +
> > +   if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
> > +           return 1;
> > +
> > +   return 0;
> > +}
> > +
> > +static void spear13xx_pcie_host_init(struct pcie_port *pp) {
> > +   spear13xx_pcie_establish_link(pp);
> > +   spear13xx_pcie_enable_interrupts(pp);
> > +}
> > +
> > +static struct pcie_host_ops spear13xx_pcie_host_ops = {
> > +   .link_up = spear13xx_pcie_link_up,
> > +   .host_init = spear13xx_pcie_host_init, };
> > +
> > +static int add_pcie_port(struct pcie_port *pp, struct platform_device
> > +*pdev) {
> > +   struct device *dev = &pdev->dev;
> > +   int ret;
> > +
> > +   pp->irq = platform_get_irq(pdev, 0);
> > +   if (!pp->irq) {
> > +           dev_err(dev, "failed to get irq\n");
> > +           return -ENODEV;
> > +   }
> > +   ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
> > +                           IRQF_SHARED, "spear1340-pcie", pp);
> > +   if (ret) {
> > +           dev_err(dev, "failed to request irq\n");
>
> Please include the IRQ number in this message.
>
> > +           return ret;
> > +   }
> > +
> > +   pp->root_bus_nr = -1;
> > +   pp->ops = &spear13xx_pcie_host_ops;
> > +
> > +   spin_lock_init(&pp->conf_lock);
> > +   ret = dw_pcie_host_init(pp);
> > +   if (ret) {
> > +           dev_err(dev, "failed to initialize host\n");
> > +           return ret;
> > +   }
> > +
> > +   return 0;
> > +}
> > +
> > +static int __init spear13xx_pcie_probe(struct platform_device *pdev)
> > +{
> > +   struct spear13xx_pcie *spear13xx_pcie;
> > +   struct pcie_port *pp;
> > +   struct device *dev = &pdev->dev;
> > +   struct device_node *np = pdev->dev.of_node;
> > +   struct resource *dbi_base;
> > +   int ret;
> > +
> > +   spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
> > +                           GFP_KERNEL);
> > +   if (!spear13xx_pcie) {
> > +           dev_err(dev, "no memory for SPEAr13xx pcie\n");
> > +           return -ENOMEM;
> > +   }
> > +
> > +   spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> > +   if (IS_ERR(spear13xx_pcie->phy)) {
> > +           ret = PTR_ERR(spear13xx_pcie->phy);
> > +           switch (ret) {
> > +           case -EPROBE_DEFER:
> > +                   dev_info(dev, "probe deferred\n");
> > +                   return ret;
> > +           default:
> > +                   dev_err(dev, "couldn't get pcie-phy\n");
> > +                   return ret;
> > +           }
>
> This would be slightly simpler (your choice):
>
>       if (ret == -EPROBE_DEFER)
>               dev_info(...)
>       else
>               dev_err(...)
>       return ret;
>
> > +   }
> > +
> > +   phy_init(spear13xx_pcie->phy);
> > +
> > +   spear13xx_pcie->clk = devm_clk_get(dev, NULL);
> > +   if (IS_ERR(spear13xx_pcie->clk)) {
> > +           dev_err(dev, "couldn't get clk for pcie\n");
> > +           return PTR_ERR(spear13xx_pcie->clk);
> > +   }
> > +   ret = clk_prepare_enable(spear13xx_pcie->clk);
> > +   if (ret) {
> > +           dev_err(dev, "couldn't enable clk for pcie\n");
> > +           return ret;
> > +   }
> > +
> > +   pp = &spear13xx_pcie->pp;
> > +
> > +   pp->dev = dev;
> > +
> > +   dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +   pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
> > +   if (IS_ERR(pp->dbi_base)) {
> > +           dev_err(dev, "couldn't remap dbi base\n");
>
> Please include the dbi_base address in the message.
>
> > +           ret = PTR_ERR(pp->dbi_base);
> > +           goto fail_clk;
> > +   }
> > +   spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
> > +
> > +   if (of_property_read_bool(np, "st,pcie-is-gen1"))
> > +           spear13xx_pcie->is_gen1 = true;
> > +
> > +   ret = add_pcie_port(pp, pdev);
> > +   if (ret < 0)
> > +           goto fail_clk;
> > +
> > +   platform_set_drvdata(pdev, spear13xx_pcie);
> > +   return 0;
> > +
> > +fail_clk:
> > +   clk_disable_unprepare(spear13xx_pcie->clk);
> > +
> > +   return ret;
> > +}
> > +
> > +static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
> > +{
> > +   struct spear13xx_pcie *spear13xx_pcie =
> platform_get_drvdata(pdev);
> > +
> > +   clk_disable_unprepare(spear13xx_pcie->clk);
> > +
> > +   phy_exit(spear13xx_pcie->phy);
> > +
> > +   return 0;
> > +}
> > +
> > +static const struct of_device_id spear13xx_pcie_of_match[] = {
> > +   { .compatible = "st,spear1340-pcie", },
> > +   {},
> > +};
> > +MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
> > +
> > +static struct platform_driver spear13xx_pcie_driver = {
> > +   .probe          = spear13xx_pcie_probe,
> > +   .remove         = spear13xx_pcie_remove,
> > +   .driver = {
> > +           .name   = "spear-pcie",
> > +           .owner  = THIS_MODULE,
> > +           .of_match_table =
> of_match_ptr(spear13xx_pcie_of_match),
> > +   },
> > +};
> > +
> > +/* SPEAr13xx PCIe driver does not allow module unload */
> > +
> > +static int __init pcie_init(void)
> > +{
> > +   return platform_driver_register(&spear13xx_pcie_driver);
> > +}
> > +module_init(pcie_init);
> > +
> > +MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host
> > +controller driver"); MODULE_AUTHOR("Pratyush Anand
> > +<pratyush.anand@st.com>"); MODULE_LICENSE("GPL v2");
> > --
> > 1.7.0.1
> >
> > --
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