From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from quartz.orcorp.ca ([184.70.90.242]:37485 "EHLO quartz.orcorp.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751320AbaEOUwW (ORCPT ); Thu, 15 May 2014 16:52:22 -0400 Date: Thu, 15 May 2014 14:52:10 -0600 From: Jason Gunthorpe To: Murali Karicheri Cc: Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , "Strashko, Grygorii" , "linux-pci@vger.kernel.org" , Jingoo Han , "linux-kernel@vger.kernel.org" , "Shilimkar, Santosh" , Mohit Kumar , Bjorn Helgaas Subject: Re: [PATCH v1 5/5] pci: keystone: add pcie driver based on designware core driver Message-ID: <20140515205210.GB14722@obsidianresearch.com> References: <1400169692-9677-1-git-send-email-m-karicheri2@ti.com> <6048322.x3M3sdDEWO@wuerfel> <5374FD24.8000806@ti.com> <22200719.Jb5jnJylJH@wuerfel> <20140515183919.GC11650@obsidianresearch.com> <53751DDF.40304@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <53751DDF.40304@ti.com> Sender: linux-pci-owner@vger.kernel.org List-ID: On Thu, May 15, 2014 at 04:04:47PM -0400, Murali Karicheri wrote: > Jason What you mean by "The PCI core handles setting the maximum > read request size already" I see there is function pcie_write_mrrs() > in the drivers/pci/probe.c that reads the mps using pcie_get_mps() > and then set mrrs to mps. But this function is called only from > pcie_bus_configure_set() that is called by > pcie_bus_configure_settings() Right, that is the common code that correctly sets the MRRS that you should be using instead of quirks. > None of them gets called on ARM platform. Hmm, a cursory glance tells me the same as well. That seems to be the root problem here, ARM needs to do the PCIE setup just as much as any other arch. So, I would prefer to see you fix ARM common code to call pcie_bus_configure_settings() properly, that seems very simple and is obviously needed for any PCI-E host driver on ARM. Thoughts? Arnd? Bjorn? Jason