* [PATCH V9 1/7] pcie: Add designware wrapper driver for SPEAr13xx
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
@ 2014-07-10 7:26 ` Viresh Kumar
2014-07-10 21:39 ` Bjorn Helgaas
2014-07-10 7:26 ` [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx Viresh Kumar
` (6 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 7:26 UTC (permalink / raw)
To: arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand, Mohit Kumar, Viresh Kumar
From: Pratyush Anand <pratyush.anand@st.com>
ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip
designware PCIe controller. To make that usable, this patch adds a wrapper
driver based on existing designware driver.
Adds bindings for this new driver and update MAINTAINERS as well.
Cc: linux-pci@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
.../devicetree/bindings/pci/spear13xx-pcie.txt | 14 +
MAINTAINERS | 6 +
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 405 +++++++++++++++++++++
5 files changed, 434 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
new file mode 100644
index 0000000..49ea76d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
@@ -0,0 +1,14 @@
+SPEAr13XX PCIe DT detail:
+================================
+
+SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
+controller.
+
+Required properties:
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys : phandle to phy node associated with pcie controller
+- phy-names : must be "pcie-phy"
+- All other definitions as per generic PCI bindings
+
+ Optional properties:
+- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
diff --git a/MAINTAINERS b/MAINTAINERS
index 702ca10..443dd05 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6820,6 +6820,12 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
F: drivers/pci/host/pci-host-generic.c
+PCIE DRIVER FOR ST SPEAR13XX
+M: Mohit Kumar <mohit.kumar@st.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/pcie-spear13xx.c
+
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
L: linux-pcmcia@lists.infradead.org
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 21df477..2d8a4d0 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -46,4 +46,12 @@ config PCI_HOST_GENERIC
Say Y here if you want to support a simple generic PCI host
controller, such as the one emulated by kvmtool.
+config PCIE_SPEAR13XX
+ tristate "STMicroelectronics SPEAr PCIe controller"
+ depends on ARCH_SPEAR13XX
+ select PCIEPORTBUS
+ select PCIE_DW
+ help
+ Say Y here if you want PCIe support on SPEAr13XX SoCs.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 611ba4b..0daec79 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
+obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
new file mode 100644
index 0000000..a6fc332
--- /dev/null
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -0,0 +1,405 @@
+/*
+ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
+ *
+ * SPEAr13xx PCIe Glue Layer Source Code
+ *
+ * Copyright (C) 2010-2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ * Mohit Kumar <mohit.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include "pcie-designware.h"
+
+struct spear13xx_pcie {
+ void __iomem *app_base;
+ struct phy *phy;
+ struct clk *clk;
+ struct pcie_port pp;
+ bool is_gen1;
+};
+
+struct pcie_app_reg {
+ u32 app_ctrl_0; /* cr0 */
+ u32 app_ctrl_1; /* cr1 */
+ u32 app_status_0; /* cr2 */
+ u32 app_status_1; /* cr3 */
+ u32 msg_status; /* cr4 */
+ u32 msg_payload; /* cr5 */
+ u32 int_sts; /* cr6 */
+ u32 int_clr; /* cr7 */
+ u32 int_mask; /* cr8 */
+ u32 mst_bmisc; /* cr9 */
+ u32 phy_ctrl; /* cr10 */
+ u32 phy_status; /* cr11 */
+ u32 cxpl_debug_info_0; /* cr12 */
+ u32 cxpl_debug_info_1; /* cr13 */
+ u32 ven_msg_ctrl_0; /* cr14 */
+ u32 ven_msg_ctrl_1; /* cr15 */
+ u32 ven_msg_data_0; /* cr16 */
+ u32 ven_msg_data_1; /* cr17 */
+ u32 ven_msi_0; /* cr18 */
+ u32 ven_msi_1; /* cr19 */
+ u32 mst_rmisc; /* cr20 */
+};
+
+/* CR0 ID */
+#define RX_LANE_FLIP_EN_ID 0
+#define TX_LANE_FLIP_EN_ID 1
+#define SYS_AUX_PWR_DET_ID 2
+#define APP_LTSSM_ENABLE_ID 3
+#define SYS_ATTEN_BUTTON_PRESSED_ID 4
+#define SYS_MRL_SENSOR_STATE_ID 5
+#define SYS_PWR_FAULT_DET_ID 6
+#define SYS_MRL_SENSOR_CHGED_ID 7
+#define SYS_PRE_DET_CHGED_ID 8
+#define SYS_CMD_CPLED_INT_ID 9
+#define APP_INIT_RST_0_ID 11
+#define APP_REQ_ENTR_L1_ID 12
+#define APP_READY_ENTR_L23_ID 13
+#define APP_REQ_EXIT_L1_ID 14
+#define DEVICE_TYPE_EP (0 << 25)
+#define DEVICE_TYPE_LEP (1 << 25)
+#define DEVICE_TYPE_RC (4 << 25)
+#define SYS_INT_ID 29
+#define MISCTRL_EN_ID 30
+#define REG_TRANSLATION_ENABLE 31
+
+/* CR1 ID */
+#define APPS_PM_XMT_TURNOFF_ID 2
+#define APPS_PM_XMT_PME_ID 5
+
+/* CR3 ID */
+#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
+#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
+#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
+#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
+#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
+#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
+#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
+#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
+#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
+#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
+#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
+#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
+#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
+#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
+#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
+#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
+#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
+#define XMLH_LTSSM_STATE_L0 0x11
+#define XMLH_LTSSM_STATE_L0S 0x12
+#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
+#define XMLH_LTSSM_STATE_L1_IDLE 0x14
+#define XMLH_LTSSM_STATE_L2_IDLE 0x15
+#define XMLH_LTSSM_STATE_L2_WAKE 0x16
+#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
+#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
+#define XMLH_LTSSM_STATE_DISABLED 0x19
+#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
+#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
+#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
+#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
+#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
+#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
+#define XMLH_LTSSM_STATE_MASK 0x3F
+#define XMLH_LINK_UP (1 << 6)
+
+/* CR4 ID */
+#define CFG_MSI_EN_ID 18
+
+/* CR6 */
+#define INTA_CTRL_INT (1 << 7)
+#define INTB_CTRL_INT (1 << 8)
+#define INTC_CTRL_INT (1 << 9)
+#define INTD_CTRL_INT (1 << 10)
+#define MSI_CTRL_INT (1 << 26)
+
+/* CR19 ID */
+#define VEN_MSI_REQ_ID 11
+#define VEN_MSI_FUN_NUM_ID 8
+#define VEN_MSI_TC_ID 5
+#define VEN_MSI_VECTOR_ID 0
+#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
+
+#define PCI_CAP_ID_EXP_OFFSET 0x70
+
+#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
+
+static int spear13xx_pcie_establish_link(struct pcie_port *pp)
+{
+ u32 val;
+ int count = 0;
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+ u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+
+ if (dw_pcie_link_up(pp)) {
+ dev_err(pp->dev, "link already up\n");
+ return 0;
+ }
+
+ dw_pcie_setup_rc(pp);
+
+ /*
+ * this controller support only 128 bytes read size, however its
+ * default value in capability register is 512 bytes. So force
+ * it to 128 here.
+ */
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+ val &= ~PCI_EXP_DEVCTL_READRQ;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+
+ dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
+ dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
+
+ /*
+ * if is_gen1 is set then handle it, so that some buggy card
+ * also works
+ */
+ if (spear13xx_pcie->is_gen1) {
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+ &val);
+ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+ PCI_EXP_LNKCAP, 4, val);
+ }
+
+ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+ &val);
+ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+ PCI_EXP_LNKCTL2, 4, val);
+ }
+ }
+
+ /* enable ltssm */
+ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+ | (1 << APP_LTSSM_ENABLE_ID)
+ | ((u32)1 << REG_TRANSLATION_ENABLE),
+ &app_reg->app_ctrl_0);
+
+ /* check if the link is up or not */
+ while (!dw_pcie_link_up(pp)) {
+ mdelay(100);
+ count++;
+ if (count == 10) {
+ dev_err(pp->dev, "link Fail\n");
+ return -EINVAL;
+ }
+ }
+ dev_info(pp->dev, "link up\n");
+
+ return 0;
+}
+
+static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+ unsigned int status;
+
+ status = readl(&app_reg->int_sts);
+
+ if (status & MSI_CTRL_INT) {
+ if (!IS_ENABLED(CONFIG_PCI_MSI))
+ BUG();
+ dw_handle_msi_irq(pp);
+ }
+
+ writel(status, &app_reg->int_clr);
+
+ return IRQ_HANDLED;
+}
+
+static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+ /* Enable MSI interrupt */
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ dw_pcie_msi_init(pp);
+ writel(readl(&app_reg->int_mask) |
+ MSI_CTRL_INT, &app_reg->int_mask);
+ }
+}
+
+static int spear13xx_pcie_link_up(struct pcie_port *pp)
+{
+ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+ if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
+ return 1;
+
+ return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+ spear13xx_pcie_establish_link(pp);
+ spear13xx_pcie_enable_interrupts(pp);
+}
+
+static struct pcie_host_ops spear13xx_pcie_host_ops = {
+ .link_up = spear13xx_pcie_link_up,
+ .host_init = spear13xx_pcie_host_init,
+};
+
+static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pp->irq = platform_get_irq(pdev, 0);
+ if (!pp->irq) {
+ dev_err(dev, "failed to get irq\n");
+ return -ENODEV;
+ }
+ ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
+ IRQF_SHARED, "spear1340-pcie", pp);
+ if (ret) {
+ dev_err(dev, "failed to request irq %d\n", pp->irq);
+ return ret;
+ }
+
+ pp->root_bus_nr = -1;
+ pp->ops = &spear13xx_pcie_host_ops;
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __init spear13xx_pcie_probe(struct platform_device *pdev)
+{
+ struct spear13xx_pcie *spear13xx_pcie;
+ struct pcie_port *pp;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *dbi_base;
+ int ret;
+
+ spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
+ if (!spear13xx_pcie) {
+ dev_err(dev, "no memory for SPEAr13xx pcie\n");
+ return -ENOMEM;
+ }
+
+ spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
+ if (IS_ERR(spear13xx_pcie->phy)) {
+ ret = PTR_ERR(spear13xx_pcie->phy);
+ if (ret == -EPROBE_DEFER)
+ dev_info(dev, "probe deferred\n");
+ else
+ dev_err(dev, "couldn't get pcie-phy\n");
+ return ret;
+ }
+
+ phy_init(spear13xx_pcie->phy);
+
+ spear13xx_pcie->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(spear13xx_pcie->clk)) {
+ dev_err(dev, "couldn't get clk for pcie\n");
+ return PTR_ERR(spear13xx_pcie->clk);
+ }
+ ret = clk_prepare_enable(spear13xx_pcie->clk);
+ if (ret) {
+ dev_err(dev, "couldn't enable clk for pcie\n");
+ return ret;
+ }
+
+ pp = &spear13xx_pcie->pp;
+
+ pp->dev = dev;
+
+ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
+ if (IS_ERR(pp->dbi_base)) {
+ dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
+ ret = PTR_ERR(pp->dbi_base);
+ goto fail_clk;
+ }
+ spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
+
+ if (of_property_read_bool(np, "st,pcie-is-gen1"))
+ spear13xx_pcie->is_gen1 = true;
+
+ ret = add_pcie_port(pp, pdev);
+ if (ret < 0)
+ goto fail_clk;
+
+ platform_set_drvdata(pdev, spear13xx_pcie);
+ return 0;
+
+fail_clk:
+ clk_disable_unprepare(spear13xx_pcie->clk);
+
+ return ret;
+}
+
+static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
+{
+ struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(spear13xx_pcie->clk);
+
+ phy_exit(spear13xx_pcie->phy);
+
+ return 0;
+}
+
+static const struct of_device_id spear13xx_pcie_of_match[] = {
+ { .compatible = "st,spear1340-pcie", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
+
+static struct platform_driver spear13xx_pcie_driver = {
+ .probe = spear13xx_pcie_probe,
+ .remove = spear13xx_pcie_remove,
+ .driver = {
+ .name = "spear-pcie",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
+ },
+};
+
+/* SPEAr13xx PCIe driver does not allow module unload */
+
+static int __init pcie_init(void)
+{
+ return platform_driver_register(&spear13xx_pcie_driver);
+}
+module_init(pcie_init);
+
+MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
--
2.0.0.rc2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH V9 1/7] pcie: Add designware wrapper driver for SPEAr13xx
2014-07-10 7:26 ` [PATCH V9 1/7] pcie: Add designware wrapper driver for SPEAr13xx Viresh Kumar
@ 2014-07-10 21:39 ` Bjorn Helgaas
2014-07-11 4:04 ` Viresh Kumar
2014-07-14 5:01 ` Viresh Kumar
0 siblings, 2 replies; 23+ messages in thread
From: Bjorn Helgaas @ 2014-07-10 21:39 UTC (permalink / raw)
To: Viresh Kumar
Cc: arnd, olof, linux-arm-kernel, spear-devel, b.zolnierkie, mark,
linux-pci, Pratyush Anand, Mohit Kumar
I guess I'm obsessive, but I think it's nice when people run
"git log --oneline" on the file or directory they're changing,
and then follow the existing style.
In this case, that would lead to a subject line like:
PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx
On Thu, Jul 10, 2014 at 12:56:32PM +0530, Viresh Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip
> designware PCIe controller. To make that usable, this patch adds a wrapper
> driver based on existing designware driver.
>
> Adds bindings for this new driver and update MAINTAINERS as well.
>
> Cc: linux-pci@vger.kernel.org
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> Acked-by: Jingoo Han <jg1.han@samsung.com>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 702ca10..443dd05 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6820,6 +6820,12 @@ S: Maintained
> F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
> F: drivers/pci/host/pci-host-generic.c
>
> +PCIE DRIVER FOR ST SPEAR13XX
> +M: Mohit Kumar <mohit.kumar@st.com>
> +L: linux-pci@vger.kernel.org
> +S: Maintained
> +F: drivers/pci/host/pcie-spear13xx.c
Wildcards work here, so you could follow the lead of IMX6, MVEBU, RCAR,
and DESIGNWARE and use:
F: drivers/pci/host/*spear*
> --- /dev/null
> +++ b/drivers/pci/host/pcie-spear13xx.c
> ...
> +#define PCI_CAP_ID_EXP_OFFSET 0x70
A nit, but I'd use a name like EXP_CAP_ID_OFFSET to make it
more clear that this is specific to SPEAr, not something from
the PCI specs.
Bjorn
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V9 1/7] pcie: Add designware wrapper driver for SPEAr13xx
2014-07-10 21:39 ` Bjorn Helgaas
@ 2014-07-11 4:04 ` Viresh Kumar
2014-07-14 5:01 ` Viresh Kumar
1 sibling, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-11 4:04 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush Anand, Mohit Kumar
On 11 July 2014 03:09, Bjorn Helgaas <bhelgaas@google.com> wrote:
> I guess I'm obsessive, but I think it's nice when people run
> "git log --oneline" on the file or directory they're changing,
> and then follow the existing style.
>
> In this case, that would lead to a subject line like:
>
> PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx
Correct.
> On Thu, Jul 10, 2014 at 12:56:32PM +0530, Viresh Kumar wrote:
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 702ca10..443dd05 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -6820,6 +6820,12 @@ S: Maintained
>> F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
>> F: drivers/pci/host/pci-host-generic.c
>>
>> +PCIE DRIVER FOR ST SPEAR13XX
>> +M: Mohit Kumar <mohit.kumar@st.com>
>> +L: linux-pci@vger.kernel.org
>> +S: Maintained
>> +F: drivers/pci/host/pcie-spear13xx.c
>
> Wildcards work here, so you could follow the lead of IMX6, MVEBU, RCAR,
> and DESIGNWARE and use:
>
> F: drivers/pci/host/*spear*
Ok.
>> --- /dev/null
>> +++ b/drivers/pci/host/pcie-spear13xx.c
>> ...
>> +#define PCI_CAP_ID_EXP_OFFSET 0x70
>
> A nit, but I'd use a name like EXP_CAP_ID_OFFSET to make it
> more clear that this is specific to SPEAr, not something from
> the PCI specs.
Sure.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V9 1/7] pcie: Add designware wrapper driver for SPEAr13xx
2014-07-10 21:39 ` Bjorn Helgaas
2014-07-11 4:04 ` Viresh Kumar
@ 2014-07-14 5:01 ` Viresh Kumar
1 sibling, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-14 5:01 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush Anand, Mohit Kumar
On 11 July 2014 03:09, Bjorn Helgaas <bhelgaas@google.com> wrote:
> I guess I'm obsessive, but I think it's nice when people run
> "git log --oneline" on the file or directory they're changing,
> and then follow the existing style.
>
> In this case, that would lead to a subject line like:
>
> PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx
>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 702ca10..443dd05 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -6820,6 +6820,12 @@ S: Maintained
>> F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
>> F: drivers/pci/host/pci-host-generic.c
>>
>> +PCIE DRIVER FOR ST SPEAR13XX
>> +M: Mohit Kumar <mohit.kumar@st.com>
>> +L: linux-pci@vger.kernel.org
>> +S: Maintained
>> +F: drivers/pci/host/pcie-spear13xx.c
>
> Wildcards work here, so you could follow the lead of IMX6, MVEBU, RCAR,
> and DESIGNWARE and use:
>
> F: drivers/pci/host/*spear*
>
>> --- /dev/null
>> +++ b/drivers/pci/host/pcie-spear13xx.c
>> ...
>> +#define PCI_CAP_ID_EXP_OFFSET 0x70
>
> A nit, but I'd use a name like EXP_CAP_ID_OFFSET to make it
> more clear that this is specific to SPEAr, not something from
> the PCI specs.
Hi Bjorn,
So this is how the diff looks like over this patch:
diff --git a/MAINTAINERS b/MAINTAINERS
index 443dd05..766948e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6824,7 +6824,7 @@ PCIE DRIVER FOR ST SPEAR13XX
M: Mohit Kumar <mohit.kumar@st.com>
L: linux-pci@vger.kernel.org
S: Maintained
-F: drivers/pci/host/pcie-spear13xx.c
+F: drivers/pci/host/*spear*
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
diff --git a/drivers/pci/host/pcie-spear13xx.c
b/drivers/pci/host/pcie-spear13xx.c
index a6fc332..99738e4 100644
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -139,7 +139,7 @@ struct pcie_app_reg {
#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
-#define PCI_CAP_ID_EXP_OFFSET 0x70
+#define EXP_CAP_ID_OFFSET 0x70
#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
@@ -149,7 +149,7 @@ static int spear13xx_pcie_establish_link(struct
pcie_port *pp)
int count = 0;
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
- u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+ u32 exp_cap_off = EXP_CAP_ID_OFFSET;
if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "link already up\n");
And the subject looks like this now:
PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx
I may skip sending a V10 for this and directly send a pull request as
there aren't any significant changes suggested in V9.
Thanks.
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
2014-07-10 7:26 ` [PATCH V9 1/7] pcie: Add designware wrapper driver for SPEAr13xx Viresh Kumar
@ 2014-07-10 7:26 ` Viresh Kumar
2014-07-10 13:17 ` Kishon Vijay Abraham I
2014-07-10 7:26 ` [PATCH V9 3/7] ARM: SPEAr13xx: Fix pcie clock name Viresh Kumar
` (5 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 7:26 UTC (permalink / raw)
To: arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand, Kishon Vijay Abraham I, Viresh Kumar
From: Pratyush Anand <pratyush.anand@st.com>
ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as
'miphy') for PCIe and SATA. This patch adds drivers for these miphys.
This also adds proper bindings for miphys.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
.../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 +
.../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +
drivers/phy/Kconfig | 12 +
drivers/phy/Makefile | 2 +
drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++++++++
drivers/phy/phy-spear1340-miphy.c | 302 +++++++++++++++++++++
6 files changed, 613 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
create mode 100644 drivers/phy/phy-spear1310-miphy.c
create mode 100644 drivers/phy/phy-spear1340-miphy.c
diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
new file mode 100644
index 0000000..b9b281a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
@@ -0,0 +1,12 @@
+ST SPEAr1310-miphy DT detail
+===================================
+
+SPEAr1310-miphy is a phy controller supporting PCIe and SATA.
+
+Required properties:
+- compatible : should be "st,spear1310-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - cell[1]: 0 if phy used for SATA, 1 for PCIe.
diff --git a/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
new file mode 100644
index 0000000..7eb5335
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
@@ -0,0 +1,11 @@
+ST SPEAr1340-miphy DT detail
+===================================
+
+SPEAr1340-miphy is a phy controller supporting PCIe and SATA.
+
+Required properties:
+- compatible : should be "st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - cell[1]: 0 if phy used for SATA, 1 for PCIe.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..e8f8a2d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,16 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_ST_SPEAR1310_MIPHY
+ tristate "ST SPEAR1310-MIPHY driver"
+ select GENERIC_PHY
+ help
+ Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA.
+
+config PHY_ST_SPEAR1340_MIPHY
+ tristate "ST SPEAR1340-MIPHY driver"
+ select GENERIC_PHY
+ help
+ Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d39609b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
+obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
+obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-spear1310-miphy.c b/drivers/phy/phy-spear1310-miphy.c
new file mode 100644
index 0000000..c58c869
--- /dev/null
+++ b/drivers/phy/phy-spear1310-miphy.c
@@ -0,0 +1,274 @@
+/*
+ * ST SPEAr1310-miphy driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ * Mohit Kumar <mohit.kumar@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG 0x3A4
+ #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
+ #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
+ #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
+ #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
+ #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
+ #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
+ #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
+ #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
+ #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
+ #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
+ #define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20)
+ #define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19)
+ #define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18)
+ #define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17)
+ #define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16)
+ #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11)
+ #define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10)
+ #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9)
+ #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8)
+ #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7)
+ #define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6)
+ #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5)
+ #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4)
+ #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3)
+ #define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2)
+ #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1)
+ #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0)
+
+ #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
+ #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+ BIT((x + 29)))
+ #define SPEAR1310_PCIE_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+ SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+ #define SPEAR1310_SATA_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+ SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
+ #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
+ #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28)
+ #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
+ #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15)
+ #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
+ #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
+
+enum spear1310_miphy_mode {
+ SATA,
+ PCIE,
+};
+
+struct spear1310_miphy_priv {
+ /* instance id of this phy */
+ u32 id;
+ /* phy mode: 0 for SATA 1 for PCIe */
+ enum spear1310_miphy_mode mode;
+ /* regmap for any soc specific misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+};
+
+static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv)
+{
+ u32 val;
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+ switch (priv->id) {
+ case 0:
+ val = SPEAR1310_PCIE_CFG_VAL(0);
+ break;
+ case 1:
+ val = SPEAR1310_PCIE_CFG_VAL(1);
+ break;
+ case 2:
+ val = SPEAR1310_PCIE_CFG_VAL(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(priv->id), val);
+
+ return 0;
+}
+
+static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+ return 0;
+}
+
+static int spear1310_miphy_init(struct phy *phy)
+{
+ struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == PCIE)
+ ret = spear1310_miphy_pcie_init(priv);
+
+ return ret;
+}
+
+static int spear1310_miphy_exit(struct phy *phy)
+{
+ struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == PCIE)
+ ret = spear1310_miphy_pcie_exit(priv);
+
+ return ret;
+}
+
+static const struct of_device_id spear1310_miphy_of_match[] = {
+ { .compatible = "st,spear1310-miphy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match);
+
+static struct phy_ops spear1310_miphy_ops = {
+ .init = spear1310_miphy_init,
+ .exit = spear1310_miphy_exit,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *spear1310_miphy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct spear1310_miphy_priv *priv = dev_get_drvdata(dev);
+
+ if (args->args_count < 1) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ priv->mode = args->args[0];
+
+ if (priv->mode != SATA && priv->mode != PCIE) {
+ dev_err(dev, "DT did not pass correct phy mode\n");
+ return NULL;
+ }
+
+ return priv->phy;
+}
+
+static int spear1310_miphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spear1310_miphy_priv *priv;
+ struct phy_provider *phy_provider;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(dev, "can't alloc spear1310_miphy private date memory\n");
+ return -ENOMEM;
+ }
+
+ priv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(priv->misc)) {
+ dev_err(dev, "failed to find misc regmap\n");
+ return PTR_ERR(priv->misc);
+ }
+
+ if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) {
+ dev_err(dev, "failed to find phy id\n");
+ return -EINVAL;
+ }
+
+ priv->phy = devm_phy_create(dev, &spear1310_miphy_ops, NULL);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ dev_set_drvdata(dev, priv);
+ phy_set_drvdata(priv->phy, priv);
+
+ phy_provider =
+ devm_of_phy_provider_register(dev, spear1310_miphy_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static struct platform_driver spear1310_miphy_driver = {
+ .probe = spear1310_miphy_probe,
+ .driver = {
+ .name = "spear1310-miphy",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(spear1310_miphy_of_match),
+ },
+};
+
+static int __init spear1310_miphy_phy_init(void)
+{
+ return platform_driver_register(&spear1310_miphy_driver);
+}
+module_init(spear1310_miphy_phy_init);
+
+static void __exit spear1310_miphy_phy_exit(void)
+{
+ platform_driver_unregister(&spear1310_miphy_driver);
+}
+module_exit(spear1310_miphy_phy_exit);
+
+MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-spear1340-miphy.c b/drivers/phy/phy-spear1340-miphy.c
new file mode 100644
index 0000000..5e39231
--- /dev/null
+++ b/drivers/phy/phy-spear1340-miphy.c
@@ -0,0 +1,302 @@
+/*
+ * ST spear1340-miphy driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ * Mohit Kumar <mohit.kumar@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG 0x100
+ #define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11)
+#define SPEAR1340_PCM_WKUP_CFG 0x104
+#define SPEAR1340_SWITCH_CTR 0x108
+
+#define SPEAR1340_PERIP1_SW_RST 0x318
+ #define SPEAR1340_PERIP1_SW_RSATA BIT(12)
+#define SPEAR1340_PERIP2_SW_RST 0x31C
+#define SPEAR1340_PERIP3_SW_RST 0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG 0x424
+ /* PCIE CFG MASks */
+ #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11)
+ #define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10)
+ #define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9)
+ #define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8)
+ #define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4)
+ #define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3)
+ #define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2)
+ #define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1)
+ #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
+ #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
+ #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
+ #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+ SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+ SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+ SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+ SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+ #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
+ SPEAR1340_SATA_CFG_PM_CLK_EN | \
+ SPEAR1340_SATA_CFG_POWERUP_RESET | \
+ SPEAR1340_SATA_CFG_RX_CLK_EN | \
+ SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG 0x428
+ #define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
+ #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+enum spear1340_miphy_mode {
+ SATA,
+ PCIE,
+};
+
+struct spear1340_miphy_priv {
+ /* phy mode: 0 for SATA 1 for PCIe */
+ enum spear1340_miphy_mode mode;
+ /* regmap for any soc specific misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+};
+
+static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK,
+ SPEAR1340_SATA_CFG_VAL);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+ /* Switch on sata power domain */
+ regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ msleep(20);
+ /* Disable PCIE SATA Controller reset */
+ regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RSATA, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_miphy_sata_exit(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+ /* Enable PCIE SATA Controller reset */
+ regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RSATA,
+ SPEAR1340_PERIP1_SW_RSATA);
+ msleep(20);
+ /* Switch off sata power domain */
+ regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_miphy_pcie_init(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK,
+ SPEAR1340_PCIE_CFG_VAL);
+
+ return 0;
+}
+
+static int spear1340_miphy_pcie_exit(struct spear1340_miphy_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+ return 0;
+}
+
+static int spear1340_miphy_init(struct phy *phy)
+{
+ struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_init(priv);
+ else if (priv->mode == PCIE)
+ ret = spear1340_miphy_pcie_init(priv);
+
+ return ret;
+}
+
+static int spear1340_miphy_exit(struct phy *phy)
+{
+ struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_exit(priv);
+ else if (priv->mode == PCIE)
+ ret = spear1340_miphy_pcie_exit(priv);
+
+ return ret;
+}
+
+static const struct of_device_id spear1340_miphy_of_match[] = {
+ { .compatible = "st,spear1340-miphy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, spear1340_miphy_of_match);
+
+static struct phy_ops spear1340_miphy_ops = {
+ .init = spear1340_miphy_init,
+ .exit = spear1340_miphy_exit,
+ .owner = THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int spear1340_miphy_suspend(struct device *dev)
+{
+ struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_exit(priv);
+
+ return ret;
+}
+
+static int spear1340_miphy_resume(struct device *dev)
+{
+ struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = spear1340_miphy_sata_init(priv);
+
+ return ret;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(spear1340_miphy_pm_ops, spear1340_miphy_suspend,
+ spear1340_miphy_resume);
+
+static struct phy *spear1340_miphy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+
+ if (args->args_count < 1) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ priv->mode = args->args[0];
+
+ if (priv->mode != SATA && priv->mode != PCIE) {
+ dev_err(dev, "DT did not pass correct phy mode\n");
+ return NULL;
+ }
+
+ return priv->phy;
+}
+
+static int spear1340_miphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spear1340_miphy_priv *priv;
+ struct phy_provider *phy_provider;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(dev, "can't alloc spear1340_miphy private date memory\n");
+ return -ENOMEM;
+ }
+
+ priv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(priv->misc)) {
+ dev_err(dev, "failed to find misc regmap\n");
+ return PTR_ERR(priv->misc);
+ }
+
+ priv->phy = devm_phy_create(dev, &spear1340_miphy_ops, NULL);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ dev_set_drvdata(dev, priv);
+ phy_set_drvdata(priv->phy, priv);
+
+ phy_provider =
+ devm_of_phy_provider_register(dev, spear1340_miphy_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static struct platform_driver spear1340_miphy_driver = {
+ .probe = spear1340_miphy_probe,
+ .driver = {
+ .name = "spear1340-miphy",
+ .owner = THIS_MODULE,
+ .pm = &spear1340_miphy_pm_ops,
+ .of_match_table = of_match_ptr(spear1340_miphy_of_match),
+ },
+};
+
+static int __init spear1340_miphy_phy_init(void)
+{
+ return platform_driver_register(&spear1340_miphy_driver);
+}
+module_init(spear1340_miphy_phy_init);
+
+static void __exit spear1340_miphy_phy_exit(void)
+{
+ platform_driver_unregister(&spear1340_miphy_driver);
+}
+module_exit(spear1340_miphy_phy_exit);
+
+MODULE_DESCRIPTION("ST SPEAR1340-MIPHY driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
--
2.0.0.rc2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 7:26 ` [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx Viresh Kumar
@ 2014-07-10 13:17 ` Kishon Vijay Abraham I
2014-07-10 13:30 ` Viresh Kumar
2014-07-14 5:31 ` Viresh Kumar
0 siblings, 2 replies; 23+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-10 13:17 UTC (permalink / raw)
To: Viresh Kumar, arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand
Hi,
On Thursday 10 July 2014 12:56 PM, Viresh Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as
> 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.
>
> This also adds proper bindings for miphys.
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 +
> .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +
> drivers/phy/Kconfig | 12 +
> drivers/phy/Makefile | 2 +
> drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++++++++
> drivers/phy/phy-spear1340-miphy.c | 302 +++++++++++++++++++++
Please send separate patche for each driver.
> 6 files changed, 613 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
> create mode 100644 Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
> create mode 100644 drivers/phy/phy-spear1310-miphy.c
> create mode 100644 drivers/phy/phy-spear1340-miphy.c
>
> diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
> new file mode 100644
> index 0000000..b9b281a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
We generally create a single document for a SoC vendor. So just use st-phy.txt.
> @@ -0,0 +1,12 @@
> +ST SPEAr1310-miphy DT detail
> +===================================
> +
> +SPEAr1310-miphy is a phy controller supporting PCIe and SATA.
> +
> +Required properties:
> +- compatible : should be "st,spear1310-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> + - cell[1]: 0 if phy used for SATA, 1 for PCIe.
> diff --git a/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
> new file mode 100644
> index 0000000..7eb5335
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
use st-phy.txt for this.
> @@ -0,0 +1,11 @@
> +ST SPEAr1340-miphy DT detail
> +===================================
> +
> +SPEAr1340-miphy is a phy controller supporting PCIe and SATA.
> +
> +Required properties:
> +- compatible : should be "st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- #phy-cells : from the generic PHY bindings, must be 1.
> + - cell[1]: 0 if phy used for SATA, 1 for PCIe.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 16a2f06..e8f8a2d 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -178,4 +178,16 @@ config PHY_XGENE
> help
> This option enables support for APM X-Gene SoC multi-purpose PHY.
>
..
<snip>
.
.
> +
> +static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK,
> + SPEAR1340_SATA_CFG_VAL);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> + /* Switch on sata power domain */
> + regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> + msleep(20);
> + /* Disable PCIE SATA Controller reset */
> + regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RSATA, 0);
> + msleep(20);
Please add a comment for all delays added.
> +
> + return 0;
> +}
> +
> +static int spear1340_miphy_sata_exit(struct spear1340_miphy_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> + /* Enable PCIE SATA Controller reset */
> + regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RSATA,
> + SPEAR1340_PERIP1_SW_RSATA);
> + msleep(20);
> + /* Switch off sata power domain */
> + regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> + msleep(20);
ditto.
> +
> + return 0;
> +}
> +
> +static int spear1340_miphy_pcie_init(struct spear1340_miphy_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK,
> + SPEAR1340_PCIE_CFG_VAL);
> +
> + return 0;
> +}
> +
> +static int spear1340_miphy_pcie_exit(struct spear1340_miphy_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> +
> + return 0;
> +}
> +
> +static int spear1340_miphy_init(struct phy *phy)
> +{
> + struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = spear1340_miphy_sata_init(priv);
> + else if (priv->mode == PCIE)
> + ret = spear1340_miphy_pcie_init(priv);
> +
> + return ret;
> +}
> +
> +static int spear1340_miphy_exit(struct phy *phy)
> +{
> + struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = spear1340_miphy_sata_exit(priv);
> + else if (priv->mode == PCIE)
> + ret = spear1340_miphy_pcie_exit(priv);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id spear1340_miphy_of_match[] = {
> + { .compatible = "st,spear1340-miphy" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, spear1340_miphy_of_match);
> +
> +static struct phy_ops spear1340_miphy_ops = {
> + .init = spear1340_miphy_init,
> + .exit = spear1340_miphy_exit,
> + .owner = THIS_MODULE,
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int spear1340_miphy_suspend(struct device *dev)
> +{
> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = spear1340_miphy_sata_exit(priv);
Shouldn't this be spear1340_miphy_init()?
> +
> + return ret;
> +}
> +
> +static int spear1340_miphy_resume(struct device *dev)
> +{
> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = spear1340_miphy_sata_init(priv);
And here spear1340_miphy_exit()? Why only for sata phys?
> +
> + return ret;
> +}
Thanks
Kishon
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 13:17 ` Kishon Vijay Abraham I
@ 2014-07-10 13:30 ` Viresh Kumar
2014-07-10 13:32 ` Kishon Vijay Abraham I
` (3 more replies)
2014-07-14 5:31 ` Viresh Kumar
1 sibling, 4 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 13:30 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush Anand
On 10 July 2014 18:47, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> On Thursday 10 July 2014 12:56 PM, Viresh Kumar wrote:
>> From: Pratyush Anand <pratyush.anand@st.com>
>>
>> ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as
>> 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.
>>
>> This also adds proper bindings for miphys.
>>
>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
>> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
>> ---
>> .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 +
>> .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +
>> drivers/phy/Kconfig | 12 +
>> drivers/phy/Makefile | 2 +
>> drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++++++++
>> drivers/phy/phy-spear1340-miphy.c | 302 +++++++++++++++++++++
>
> Please send separate patche for each driver.
These were both around SPEAr and were on the same lines.
So sending these in a single patch shouldn't be a big issue I believe.
In case another version is required, I may do it.
>> diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>> new file mode 100644
>> index 0000000..b9b281a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>
> We generally create a single document for a SoC vendor. So just use st-phy.txt.
Probably yes.
> <snip>
Please keep line containing file names while removing stuff, makes it easy
to locate code.
>> +
>> +static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
>> +{
>> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
>> + SPEAR1340_PCIE_SATA_CFG_MASK,
>> + SPEAR1340_SATA_CFG_VAL);
>> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
>> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>> + /* Switch on sata power domain */
>> + regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
>> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
>> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
>> + msleep(20);
>> + /* Disable PCIE SATA Controller reset */
>> + regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
>> + SPEAR1340_PERIP1_SW_RSATA, 0);
>> + msleep(20);
>
> Please add a comment for all delays added.
@Pratyush/Mohit: please let me know what to add here.
>> +#ifdef CONFIG_PM_SLEEP
>> +static int spear1340_miphy_suspend(struct device *dev)
>> +{
>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>> + int ret = 0;
>> +
>> + if (priv->mode == SATA)
>> + ret = spear1340_miphy_sata_exit(priv);
>
> Shouldn't this be spear1340_miphy_init()?
>> +
>> + return ret;
>> +}
>> +
>> +static int spear1340_miphy_resume(struct device *dev)
>> +{
>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>> + int ret = 0;
>> +
>> + if (priv->mode == SATA)
>> + ret = spear1340_miphy_sata_init(priv);
>
> And here spear1340_miphy_exit()? Why only for sata phys?
@Mohit/Pratyush ??
Thanks Kishon for another round of review :)
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 13:30 ` Viresh Kumar
@ 2014-07-10 13:32 ` Kishon Vijay Abraham I
2014-07-11 8:32 ` Kishon Vijay Abraham I
` (2 subsequent siblings)
3 siblings, 0 replies; 23+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-10 13:32 UTC (permalink / raw)
To: Viresh Kumar
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush Anand
On Thursday 10 July 2014 07:00 PM, Viresh Kumar wrote:
> On 10 July 2014 18:47, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>> On Thursday 10 July 2014 12:56 PM, Viresh Kumar wrote:
>>> From: Pratyush Anand <pratyush.anand@st.com>
>>>
>>> ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as
>>> 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.
>>>
>>> This also adds proper bindings for miphys.
>>>
>>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
>>> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
>>> ---
>>> .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 +
>>> .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +
>>> drivers/phy/Kconfig | 12 +
>>> drivers/phy/Makefile | 2 +
>>> drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++++++++
>>> drivers/phy/phy-spear1340-miphy.c | 302 +++++++++++++++++++++
>>
>> Please send separate patche for each driver.
>
> These were both around SPEAr and were on the same lines.
> So sending these in a single patch shouldn't be a big issue I believe.
>
> In case another version is required, I may do it.
>
>>> diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>>> new file mode 100644
>>> index 0000000..b9b281a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>>
>> We generally create a single document for a SoC vendor. So just use st-phy.txt.
>
> Probably yes.
>
>> <snip>
>
> Please keep line containing file names while removing stuff, makes it easy
> to locate code.
ah.. apologies..
>
>>> +
>>> +static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
>>> +{
>>> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> + SPEAR1340_PCIE_SATA_CFG_MASK,
>>> + SPEAR1340_SATA_CFG_VAL);
>>> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
>>> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>>> + /* Switch on sata power domain */
>>> + regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
>>> + msleep(20);
>>> + /* Disable PCIE SATA Controller reset */
>>> + regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
>>> + SPEAR1340_PERIP1_SW_RSATA, 0);
>>> + msleep(20);
>>
>> Please add a comment for all delays added.
>
> @Pratyush/Mohit: please let me know what to add here.
>
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int spear1340_miphy_suspend(struct device *dev)
>>> +{
>>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>>> + int ret = 0;
>>> +
>>> + if (priv->mode == SATA)
>>> + ret = spear1340_miphy_sata_exit(priv);
>>
>> Shouldn't this be spear1340_miphy_init()?
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static int spear1340_miphy_resume(struct device *dev)
>>> +{
>>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>>> + int ret = 0;
>>> +
>>> + if (priv->mode == SATA)
>>> + ret = spear1340_miphy_sata_init(priv);
>>
>> And here spear1340_miphy_exit()? Why only for sata phys?
>
> @Mohit/Pratyush ??
>
> Thanks Kishon for another round of review :)
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 13:30 ` Viresh Kumar
2014-07-10 13:32 ` Kishon Vijay Abraham I
@ 2014-07-11 8:32 ` Kishon Vijay Abraham I
2014-07-14 5:22 ` Mohit KUMAR DCG
2014-07-11 9:07 ` Viresh Kumar
2014-07-14 5:37 ` Viresh Kumar
3 siblings, 1 reply; 23+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-11 8:32 UTC (permalink / raw)
To: Viresh Kumar
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush Anand
On Thursday 10 July 2014 07:00 PM, Viresh Kumar wrote:
> On 10 July 2014 18:47, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>> On Thursday 10 July 2014 12:56 PM, Viresh Kumar wrote:
>>> From: Pratyush Anand <pratyush.anand@st.com>
>>>
>>> ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as
>>> 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.
>>>
>>> This also adds proper bindings for miphys.
>>>
>>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
>>> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
>>> ---
>>> .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 +
>>> .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +
>>> drivers/phy/Kconfig | 12 +
>>> drivers/phy/Makefile | 2 +
>>> drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++++++++
>>> drivers/phy/phy-spear1340-miphy.c | 302 +++++++++++++++++++++
>>
>> Please send separate patche for each driver.
>
> These were both around SPEAr and were on the same lines.
> So sending these in a single patch shouldn't be a big issue I believe.
>
> In case another version is required, I may do it.
yes please.
-Kishon
>
>>> diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>>> new file mode 100644
>>> index 0000000..b9b281a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>>
>> We generally create a single document for a SoC vendor. So just use st-phy.txt.
>
> Probably yes.
>
>> <snip>
>
> Please keep line containing file names while removing stuff, makes it easy
> to locate code.
>
>>> +
>>> +static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
>>> +{
>>> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> + SPEAR1340_PCIE_SATA_CFG_MASK,
>>> + SPEAR1340_SATA_CFG_VAL);
>>> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
>>> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>>> + /* Switch on sata power domain */
>>> + regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
>>> + msleep(20);
>>> + /* Disable PCIE SATA Controller reset */
>>> + regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
>>> + SPEAR1340_PERIP1_SW_RSATA, 0);
>>> + msleep(20);
>>
>> Please add a comment for all delays added.
>
> @Pratyush/Mohit: please let me know what to add here.
>
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int spear1340_miphy_suspend(struct device *dev)
>>> +{
>>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>>> + int ret = 0;
>>> +
>>> + if (priv->mode == SATA)
>>> + ret = spear1340_miphy_sata_exit(priv);
>>
>> Shouldn't this be spear1340_miphy_init()?
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static int spear1340_miphy_resume(struct device *dev)
>>> +{
>>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>>> + int ret = 0;
>>> +
>>> + if (priv->mode == SATA)
>>> + ret = spear1340_miphy_sata_init(priv);
>>
>> And here spear1340_miphy_exit()? Why only for sata phys?
>
> @Mohit/Pratyush ??
>
> Thanks Kishon for another round of review :)
>
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-11 8:32 ` Kishon Vijay Abraham I
@ 2014-07-14 5:22 ` Mohit KUMAR DCG
2014-07-14 5:24 ` Viresh Kumar
0 siblings, 1 reply; 23+ messages in thread
From: Mohit KUMAR DCG @ 2014-07-14 5:22 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Viresh Kumar
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush ANAND
SGVsbG8gS2lzaG9uL1ZpcmVzaCwNCg0KPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBG
cm9tOiBLaXNob24gVmlqYXkgQWJyYWhhbSBJIFttYWlsdG86a2lzaG9uQHRpLmNvbV0NCj4gU2Vu
dDogRnJpZGF5LCBKdWx5IDExLCAyMDE0IDI6MDMgUE0NCj4gVG86IFZpcmVzaCBLdW1hcg0KPiBD
YzogQXJuZCBCZXJnbWFubjsgb2xvZkBsaXhvbS5uZXQ7IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMu
aW5mcmFkZWFkLm9yZzsNCj4gc3BlYXItZGV2ZWw7IEJhcnRsb21pZWogWm9sbmllcmtpZXdpY3o7
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cm90ZToNCj4gPiBPbiAxMCBKdWx5IDIwMTQgMTg6NDcsIEtpc2hvbiBWaWpheSBBYnJhaGFtIEkg
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aXBoeV9wcml2DQo+ID4+PiArKnByaXYpIHsNCj4gPj4+ICsgICAgIHJlZ21hcF91cGRhdGVfYml0
cyhwcml2LT5taXNjLCBTUEVBUjEzNDBfUENJRV9TQVRBX0NGRywNCj4gPj4+ICsgICAgICAgICAg
ICAgICAgICAgICAgICBTUEVBUjEzNDBfUENJRV9TQVRBX0NGR19NQVNLLA0KPiA+Pj4gKyAgICAg
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IGEgY29tbWVudCBmb3IgYWxsIGRlbGF5cyBhZGRlZC4NCj4gPg0KPiA+IEBQcmF0eXVzaC9Nb2hp
dDogcGxlYXNlIGxldCBtZSBrbm93IHdoYXQgdG8gYWRkIGhlcmUuDQo+ID4NCg0KLSBJIHRoaW5r
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bmQgc28gdGhlIGNvbW1lbnQgYWJvdmUgaXQNCmlzIHZhbGlkIGZvciBib3RoIHRoZSBvcGVyYXRp
b25zLg0KDQpPdGhlcndpc2Ugd2UgY2FuIGFkZCBjb21tZW50IGxpbmUgZm9yIG1zbGVlcCgpIGxp
a2U6DQovKiBXYWl0IGZvciBTQVRBIHBvd2VyIGRvbWFpbiBvbiAqLw0KLyogV2FpdCBmb3IgU0FU
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-14 5:22 ` Mohit KUMAR DCG
@ 2014-07-14 5:24 ` Viresh Kumar
2014-07-14 5:34 ` Viresh Kumar
0 siblings, 1 reply; 23+ messages in thread
From: Viresh Kumar @ 2014-07-14 5:24 UTC (permalink / raw)
To: Mohit KUMAR DCG
Cc: Kishon Vijay Abraham I, Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush ANAND
On 14 July 2014 10:52, Mohit KUMAR DCG <Mohit.KUMAR@st.com> wrote:
> - I think we should read regmap_*() and msleep() in continuation and so the comment above it
> is valid for both the operations.
Probably not, its not obvious why a msleep() is required after regmap_*().
> Otherwise we can add comment line for msleep() like:
> /* Wait for SATA power domain on */
> /* Wait for SATA reset de-assert completion */
>
> Similarily in *_exit routine:
> /* Wait for SATA power domain off */
> /* Wait for SATA reset assert completion */
These makes sense. Will add them.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-14 5:24 ` Viresh Kumar
@ 2014-07-14 5:34 ` Viresh Kumar
0 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-14 5:34 UTC (permalink / raw)
To: Mohit KUMAR DCG
Cc: Kishon Vijay Abraham I, Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush ANAND
On 14 July 2014 10:54, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> These makes sense. Will add them.
Kishon, here is how the diff looks like now:
diff --git a/drivers/phy/phy-spear1340-miphy.c
b/drivers/phy/phy-spear1340-miphy.c
index 5e39231..8de98ad 100644
--- a/drivers/phy/phy-spear1340-miphy.c
+++ b/drivers/phy/phy-spear1340-miphy.c
@@ -101,10 +101,13 @@ static int spear1340_miphy_sata_init(struct
spear1340_miphy_priv *priv)
regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
SPEAR1340_PCM_CFG_SATA_POWER_EN,
SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ /* Wait for SATA power domain on */
msleep(20);
+
/* Disable PCIE SATA Controller reset */
regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
SPEAR1340_PERIP1_SW_RSATA, 0);
+ /* Wait for SATA reset de-assert completion */
msleep(20);
return 0;
@@ -121,10 +124,12 @@ static int spear1340_miphy_sata_exit(struct
spear1340_miphy_priv *priv)
regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
SPEAR1340_PERIP1_SW_RSATA,
SPEAR1340_PERIP1_SW_RSATA);
+ /* Wait for SATA power domain off */
msleep(20);
/* Switch off sata power domain */
regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ /* Wait for SATA reset assert completion */
msleep(20);
return 0;
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 13:30 ` Viresh Kumar
2014-07-10 13:32 ` Kishon Vijay Abraham I
2014-07-11 8:32 ` Kishon Vijay Abraham I
@ 2014-07-11 9:07 ` Viresh Kumar
2014-07-14 5:37 ` Viresh Kumar
3 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-11 9:07 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Pratyush Anand, Bartlomiej Zolnierkiewicz,
linux-pci@vger.kernel.org, spear-devel, Mark Nicholson,
Bjorn Helgaas, olof@lixom.net, Arnd Bergmann,
linux-arm-kernel@lists.infradead.org
On Thu, Jul 10, 2014 at 7:00 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int spear1340_miphy_suspend(struct device *dev)
>>> +{
>>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>>> + int ret = 0;
>>> +
>>> + if (priv->mode == SATA)
>>> + ret = spear1340_miphy_sata_exit(priv);
>>
>> Shouldn't this be spear1340_miphy_init()?
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static int spear1340_miphy_resume(struct device *dev)
>>> +{
>>> + struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
>>> + int ret = 0;
>>> +
>>> + if (priv->mode == SATA)
>>> + ret = spear1340_miphy_sata_init(priv);
>>
>> And here spear1340_miphy_exit()? Why only for sata phys?
Kishon,
I had a chat with Pratyush and this is what we came to:
init and exit are rightly placed I believe. We need to initialize from
resume and exit from suspend. That's fine right? Also this was already
part of: arch/arm/mach-spear/spear1340.c which is removed with
this set.
Regarding sata and pcie, pcie suspend isn't yet implemented and
tested. So only sata :)
For delays, need to wait for mohit. Was on leave today.
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 13:30 ` Viresh Kumar
` (2 preceding siblings ...)
2014-07-11 9:07 ` Viresh Kumar
@ 2014-07-14 5:37 ` Viresh Kumar
3 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-14 5:37 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush Anand
On 10 July 2014 19:00, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>>> drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++++++++
>>> drivers/phy/phy-spear1340-miphy.c | 302 +++++++++++++++++++++
>>
>> Please send separate patche for each driver.
>
> These were both around SPEAr and were on the same lines.
> So sending these in a single patch shouldn't be a big issue I believe.
For completeness I have still kept them together as they have a single
bindings file now. And breaking it out *may* affect readability later.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx
2014-07-10 13:17 ` Kishon Vijay Abraham I
2014-07-10 13:30 ` Viresh Kumar
@ 2014-07-14 5:31 ` Viresh Kumar
1 sibling, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-14 5:31 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Arnd Bergmann, olof@lixom.net,
linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Pratyush Anand
On 10 July 2014 18:47, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>> diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>> new file mode 100644
>> index 0000000..b9b281a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt
>
> We generally create a single document for a SoC vendor. So just use st-phy.txt.
st-phy may not be appropriate as this is specifically for SPEAr. New
binding doc looks like this:
diff --git a/Documentation/devicetree/bindings/phy/st-spear-miphy.txt
b/Documentation/devicetree/bindings/phy/st-spear-miphy.txt
new file mode 100644
index 0000000..2a6bfdc
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-spear-miphy.txt
@@ -0,0 +1,15 @@
+ST SPEAr miphy DT details
+=========================
+
+ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
+
+Required properties:
+- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - cell[1]: 0 if phy used for SATA, 1 for PCIe.
+
+Optional properties:
+- phy-id: Instance id of the phy. Only required when there are multiple phys
+ present on a implementation.
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH V9 3/7] ARM: SPEAr13xx: Fix pcie clock name
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
2014-07-10 7:26 ` [PATCH V9 1/7] pcie: Add designware wrapper driver for SPEAr13xx Viresh Kumar
2014-07-10 7:26 ` [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx Viresh Kumar
@ 2014-07-10 7:26 ` Viresh Kumar
2014-07-11 13:50 ` Mike Turquette
2014-07-10 7:26 ` [PATCH V9 4/7] ARM: SPEAr13xx: Fix static mapping table Viresh Kumar
` (4 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 7:26 UTC (permalink / raw)
To: arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand, Mike Turquette, Viresh Kumar
From: Pratyush Anand <pratyush.anand@st.com>
Follow dt clock naming convention for PCIe clocks.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
[viresh: fixed logs/cclist]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/clk/spear/spear1310_clock.c | 6 +++---
drivers/clk/spear/spear1340_clock.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.0");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.1");
+ clk_register_clkdev(clk, NULL, "b1800000.pcie");
clk_register_clkdev(clk, NULL, "b1800000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.2");
+ clk_register_clkdev(clk, NULL, "b4000000.pcie");
clk_register_clkdev(clk, NULL, "b4000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
--
2.0.0.rc2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH V9 3/7] ARM: SPEAr13xx: Fix pcie clock name
2014-07-10 7:26 ` [PATCH V9 3/7] ARM: SPEAr13xx: Fix pcie clock name Viresh Kumar
@ 2014-07-11 13:50 ` Mike Turquette
0 siblings, 0 replies; 23+ messages in thread
From: Mike Turquette @ 2014-07-11 13:50 UTC (permalink / raw)
To: Viresh Kumar, arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand, Viresh Kumar
Quoting Viresh Kumar (2014-07-10 00:26:34)
> From: Pratyush Anand <pratyush.anand@st.com>
>
> Follow dt clock naming convention for PCIe clocks.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Mike Turquette <mturquette@linaro.org>
> [viresh: fixed logs/cclist]
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/spear/spear1310_clock.c | 6 +++---
> drivers/clk/spear/spear1340_clock.c | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
> index 65894f7..4daa597 100644
> --- a/drivers/clk/spear/spear1310_clock.c
> +++ b/drivers/clk/spear/spear1310_clock.c
> @@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
> clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
> SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
> 0, &_lock);
> - clk_register_clkdev(clk, NULL, "dw_pcie.0");
> + clk_register_clkdev(clk, NULL, "b1000000.pcie");
> clk_register_clkdev(clk, NULL, "b1000000.ahci");
>
> clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
> SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
> 0, &_lock);
> - clk_register_clkdev(clk, NULL, "dw_pcie.1");
> + clk_register_clkdev(clk, NULL, "b1800000.pcie");
> clk_register_clkdev(clk, NULL, "b1800000.ahci");
>
> clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
> SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
> 0, &_lock);
> - clk_register_clkdev(clk, NULL, "dw_pcie.2");
> + clk_register_clkdev(clk, NULL, "b4000000.pcie");
> clk_register_clkdev(clk, NULL, "b4000000.ahci");
>
> clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
> diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
> index fe835c1..5a5c664 100644
> --- a/drivers/clk/spear/spear1340_clock.c
> +++ b/drivers/clk/spear/spear1340_clock.c
> @@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
> clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
> SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
> 0, &_lock);
> - clk_register_clkdev(clk, NULL, "dw_pcie");
> + clk_register_clkdev(clk, NULL, "b1000000.pcie");
> clk_register_clkdev(clk, NULL, "b1000000.ahci");
>
> clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
> --
> 2.0.0.rc2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH V9 4/7] ARM: SPEAr13xx: Fix static mapping table
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
` (2 preceding siblings ...)
2014-07-10 7:26 ` [PATCH V9 3/7] ARM: SPEAr13xx: Fix pcie clock name Viresh Kumar
@ 2014-07-10 7:26 ` Viresh Kumar
2014-07-10 7:26 ` [PATCH V9 5/7] ARM: SPEAr13xx: Add bindings and dt node for misc block Viresh Kumar
` (3 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 7:26 UTC (permalink / raw)
To: arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand, Mohit Kumar, Viresh Kumar
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr13xx was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. But pci_remap_io uses 0xFEE00000 as virtual address and so
replace 0xFE000000 with 0xF9000000.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/mach-spear/include/mach/spear.h | 4 ++--
arch/arm/mach-spear/spear13xx.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..f2d6a01 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
#ifdef CONFIG_ARCH_SPEAR13XX
#define PERIP_GRP2_BASE UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
-#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE IOMEM(0xF9800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index c9897ea..53a7614 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)
/*
* Following will create 16MB static virtual/physical mappings
* PHYSICAL VIRTUAL
- * 0xB3000000 0xFE000000
+ * 0xB3000000 0xF9000000
* 0xE0000000 0xFD000000
* 0xEC000000 0xFC000000
* 0xED000000 0xFB000000
--
2.0.0.rc2
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V9 5/7] ARM: SPEAr13xx: Add bindings and dt node for misc block
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
` (3 preceding siblings ...)
2014-07-10 7:26 ` [PATCH V9 4/7] ARM: SPEAr13xx: Fix static mapping table Viresh Kumar
@ 2014-07-10 7:26 ` Viresh Kumar
2014-07-10 7:26 ` [PATCH V9 6/7] ARM: SPEAr13xx: Add pcie and miphy DT nodes Viresh Kumar
` (2 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 7:26 UTC (permalink / raw)
To: arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand, devicetree, Viresh Kumar
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr SOCs have some miscellaneous registers which are used to configure
peripheral.
This patch adds dt node and binding information for this block.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: devicetree@vger.kernel.org
[viresh: fixed logs/cclist]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
Documentation/devicetree/bindings/arm/spear-misc.txt | 9 +++++++++
arch/arm/boot/dts/spear13xx.dtsi | 5 +++++
arch/arm/mach-spear/Kconfig | 1 +
3 files changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..cf64982
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,9 @@
+SPEAr Misc configuration
+===========================
+SPEAr SOCs have some miscellaneous registers which are used to configure
+few properties of different peripheral controllers.
+
+misc node required properties:
+
+- compatible Should be "st,spear1340-misc", "syscon".
+- reg: Address range of misc space upto 8K
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
+ misc: syscon@e0700000 {
+ compatible = "st,spear1340-misc", "syscon";
+ reg = <0xe0700000 0x1000>;
+ };
+
gpio0: gpio@e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 90df202..ba57677 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -19,6 +19,7 @@ config ARCH_SPEAR13XX
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PINCTRL
+ select MFD_SYSCON
help
Supports for ARM's SPEAR13XX family
--
2.0.0.rc2
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V9 6/7] ARM: SPEAr13xx: Add pcie and miphy DT nodes
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
` (4 preceding siblings ...)
2014-07-10 7:26 ` [PATCH V9 5/7] ARM: SPEAr13xx: Add bindings and dt node for misc block Viresh Kumar
@ 2014-07-10 7:26 ` Viresh Kumar
2014-07-10 7:26 ` [PATCH V9 7/7] ARM: SPEAr13xx: Update defconfigs Viresh Kumar
2014-07-14 5:45 ` [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
7 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 7:26 UTC (permalink / raw)
To: arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Pratyush Anand, Mohit Kumar, Viresh Kumar
From: Pratyush Anand <pratyush.anand@st.com>
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx
SoCs.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with
ahci/sata pins. By default evaluation board of both controller works in ahci
mode. Because of this, these nodes are marked "disabled" by default.
In order to use pcie controller on evaluation boards do necessary modifications
on board and enable (By replacing "disabled" with "okay") pcie and miphy from
respective 'evb' dtsi file.
Phy specific initialization was previously done from spear1340.c, which isn't
required anymore as we have separate drivers for it. Remove it.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear1310-evb.dts | 4 ++
arch/arm/boot/dts/spear1310.dtsi | 93 ++++++++++++++++++++++++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 ++
arch/arm/boot/dts/spear1340.dtsi | 30 ++++++++-
arch/arm/boot/dts/spear13xx.dtsi | 4 +-
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/spear1340.c | 125 +-----------------------------------
7 files changed, 133 insertions(+), 130 deletions(-)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
cf@b2800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..fa5f2bb 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,111 @@
#gpio-cells = <2>;
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,spear1310-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy1: miphy@eb804000 {
+ compatible = "st,spear1310-miphy";
+ reg = <0xeb804000 0x4000>;
+ misc = <&misc>;
+ phy-id = <1>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy2: miphy@eb808000 {
+ compatible = "st,spear1310-miphy";
+ reg = <0xeb808000 0x4000>;
+ misc = <&misc>;
+ phy-id = <2>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci@b1800000 {
+ ahci1: ahci@b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
+ phys = <&miphy1 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci@b4000000 {
+ ahci2: ahci@b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
+ phys = <&miphy2 0>;
+ phy-names = "sata-phy";
+ status = "disabled";
+ };
+
+ pcie0: pcie@b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 68 0x4>;
+ num-lanes = <1>;
+ phys = <&miphy0 1>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie1: pcie@b1800000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1800000 0x4000>;
+ interrupts = <0 69 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 69 0x4>;
+ num-lanes = <1>;
+ phys = <&miphy1 1>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie2: pcie@b4000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb4000000 0x4000>;
+ interrupts = <0 70 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 70 0x4>;
+ num-lanes = <1>;
+ phys = <&miphy2 1>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
dma@ea800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..e71df0f 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,38 @@
status = "disabled";
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,spear1340-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
+ status = "disabled";
+ };
+
+ pcie0: pcie@b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 0 68 0x4>;
+ num-lanes = <1>;
+ phys = <&miphy0 1>;
+ phy-names = "pcie-phy";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3a72508..a6eb543 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
- 0xb0000000 0xb0000000 0x10000000
- 0xd0000000 0xd0000000 0x02000000
+ 0x80000000 0x80000000 0x20000000
+ 0xb0000000 0xb0000000 0x22000000
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ba57677..6fd4dc8 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -20,6 +20,7 @@ config ARCH_SPEAR13XX
select HAVE_ARM_TWD if SMP
select PINCTRL
select MFD_SYSCON
+ select MIGHT_HAVE_PCI
help
Supports for ARM's SPEAR13XX family
@@ -28,12 +29,14 @@ if ARCH_SPEAR13XX
config MACH_SPEAR1310
bool "SPEAr1310 Machine support with Device Tree"
select PINCTRL_SPEAR1310
+ select PHY_ST_SPEAR1310_MIPHY
help
Supports ST SPEAr1310 machine configured via the device-tree
config MACH_SPEAR1340
bool "SPEAr1340 Machine support with Device Tree"
select PINCTRL_SPEAR1340
+ select PHY_ST_SPEAR1340_MIPHY
help
Supports ST SPEAr1340 machine configured via the device-tree
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 7b6bff7..3f3c0f1 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -13,136 +13,13 @@
#define pr_fmt(fmt) "SPEAr1340: " fmt
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
- /* PCIE CFG MASks */
- #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
- #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
- #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
- #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
- #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
- #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
- #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
- #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
- #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
- #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
- #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
- #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
- SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
- SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
- SPEAR1340_PCIE_CFG_POWERUP_RESET | \
- SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
- #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
- SPEAR1340_SATA_CFG_PM_CLK_EN | \
- SPEAR1340_SATA_CFG_POWERUP_RESET | \
- SPEAR1340_SATA_CFG_RX_CLK_EN | \
- SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
- #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
- #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
- #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_CLK_REF_DIV2 | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
- (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
- writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
- writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
- SPEAR1340_PCIE_MIPHY_CFG);
- /* Switch on sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
- /* Disable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
-
- return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
- writel(0, SPEAR1340_PCIE_SATA_CFG);
- writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
- /* Enable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
- /* Switch off sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_FREEZE)
- return 0;
-
- sata_miphy_exit(dev);
-
- return 0;
-}
-
-int sata_resume(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_THAW)
- return 0;
-
- return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
- .init = sata_miphy_init,
- .exit = sata_miphy_exit,
- .suspend = sata_suspend,
- .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
- &sata_pdata),
- {}
-};
static void __init spear1340_dt_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- spear1340_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
platform_device_register_simple("spear-cpufreq", -1, NULL, 0);
}
--
2.0.0.rc2
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V9 7/7] ARM: SPEAr13xx: Update defconfigs
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
` (5 preceding siblings ...)
2014-07-10 7:26 ` [PATCH V9 6/7] ARM: SPEAr13xx: Add pcie and miphy DT nodes Viresh Kumar
@ 2014-07-10 7:26 ` Viresh Kumar
2014-07-14 5:45 ` [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
7 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-10 7:26 UTC (permalink / raw)
To: arnd, olof
Cc: linux-arm-kernel, spear-devel, b.zolnierkie, bhelgaas, mark,
linux-pci, Mohit Kumar, Viresh Kumar
From: Mohit Kumar <mohit.kumar@st.com>
Enable PCIe, EABI, VFP and NFS configs in default configuration file for
SPEAr13xx.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/configs/spear13xx_defconfig | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..d271b26 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
# CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +92,14 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
--
2.0.0.rc2
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support
2014-07-10 7:26 [PATCH V9 0/7] ARM: SPEAr13xx: Add PCIe support Viresh Kumar
` (6 preceding siblings ...)
2014-07-10 7:26 ` [PATCH V9 7/7] ARM: SPEAr13xx: Update defconfigs Viresh Kumar
@ 2014-07-14 5:45 ` Viresh Kumar
7 siblings, 0 replies; 23+ messages in thread
From: Viresh Kumar @ 2014-07-14 5:45 UTC (permalink / raw)
To: Arnd Bergmann, olof@lixom.net, Kishon
Cc: linux-arm-kernel@lists.infradead.org, spear-devel,
Bartlomiej Zolnierkiewicz, Bjorn Helgaas, Mark Nicholson,
linux-pci@vger.kernel.org, Viresh Kumar
On 10 July 2014 12:56, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> This adds PCIe support for ARM based ST Microelectronics SPEAr13xx SoCs.
>
> V8 was here: https://lkml.org/lkml/2014/4/15/260 and just before being pulled by
> Olof this happened: https://lkml.org/lkml/2014/7/9/641.
>
> An detailed look at the patches make it clear why Olof was unhappy.
> Patches weren't in right order, groups, etc..
>
> So, this is an attempt to fix all those issues. Pushed here:
> git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux.git spear/pcie-support-v9
It may not be worth enough to send V10 as there aren't many updates.
I have provided proper diff's in response to the comments I got.
V10 is here:
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux.git
spear/pcie-support-v10
Let me know if something is still missing before I send a pull request tomorrow.
--
Viresh
^ permalink raw reply [flat|nested] 23+ messages in thread