From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: David Daney <ddaney.cavm@gmail.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Will Deacon <Will.Deacon@arm.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <Pawel.Moll@arm.com>,
Mark Rutland <Mark.Rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Marc Zyngier <Marc.Zyngier@arm.com>,
David Daney <david.daney@cavium.com>
Subject: Re: [PATCH 3/3] PCI: generic: Add support for Cavium ThunderX PCIe root complexes.
Date: Tue, 22 Sep 2015 17:05:49 +0100 [thread overview]
Message-ID: <20150922160549.GE17444@red-moon> (raw)
In-Reply-To: <1442529694-1792-4-git-send-email-ddaney.cavm@gmail.com>
On Thu, Sep 17, 2015 at 11:41:34PM +0100, David Daney wrote:
> From: David Daney <david.daney@cavium.com>
>
> The config space for external PCIe root complexes on some Cavium
> ThunderX SoCs is very similar to CAM and ECAM, but differs in the
> shift values that have to be applied to the bus and devfn numbers to
> compose that address window offset. These root complexes also have
> the interesting property that there is no root bridge, so the standard
> manner of limiting scanning to only the first device doesn't work. We
> can use the standard pci-host-generic driver if we make a minor
> addition to handle these differences, so we...
>
> Add a mapping function for ThunderX PCIe root complexes with a bus
> shift of 24 and devfn shift of 16. Ignore accesses for devices other
> than the first device on the primary bus.
>
> Document the whole thing in devicetree/bindings/pci/host-generic-pci.txt
>
> Signed-off-by: David Daney <david.daney@cavium.com>
> ---
> .../devicetree/bindings/pci/host-generic-pci.txt | 8 +++---
> drivers/pci/host/pci-host-generic.c | 29 ++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> index 105a968..a5aed0f 100644
> --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> @@ -14,9 +14,11 @@ tree bindings communicated in pci.txt:
>
> Properties of the host controller node:
>
> -- compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic"
> - depending on the layout of configuration space (CAM vs
> - ECAM respectively).
> +- compatible : One of the following with bus:devfn:reg mapped to the
> + PCI config space address window in the bit positions shown:
> + "pci-host-cam-generic" -- 'CAM' bits 16:8:0
> + "pci-host-ecam-generic" -- 'ECAM' bits 20:12:0
> + "cavium,pci-host-thunder-pem" -- bits 24:16:0
To me that's ECAM left shifted by 4. Is not it just a matter of defining
config space base address (ie reg property) differently ?
Lorenzo
>
> - device_type : Must be "pci".
>
> diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c
> index e364232..e1d8d5b 100644
> --- a/drivers/pci/host/pci-host-generic.c
> +++ b/drivers/pci/host/pci-host-generic.c
> @@ -91,6 +91,32 @@ static struct gen_pci_cfg_bus_ops gen_pci_cfg_ecam_bus_ops = {
> }
> };
>
> +static void __iomem *gen_pci_map_cfg_bus_thunder_pem(struct pci_bus *bus,
> + unsigned int devfn,
> + int where)
> +{
> + struct gen_pci *pci = bus->sysdata;
> + resource_size_t idx = bus->number - pci->cfg.bus_range->start;
> +
> + /*
> + * Thunder PEM is a PCIe RC, but without a root bridge. On
> + * the primary bus, ignore accesses for devices other than
> + * the first device.
> + */
> + if (idx == 0 && (devfn & ~7u))
> + return NULL;
> + return pci->cfg.win[idx] + ((devfn << 16) | where);
> +}
> +
> +static struct gen_pci_cfg_bus_ops gen_pci_cfg_thunder_pem_bus_ops = {
> + .bus_shift = 24,
> + .ops = {
> + .map_bus = gen_pci_map_cfg_bus_thunder_pem,
> + .read = pci_generic_config_read,
> + .write = pci_generic_config_write,
> + }
> +};
> +
> static const struct of_device_id gen_pci_of_match[] = {
> { .compatible = "pci-host-cam-generic",
> .data = &gen_pci_cfg_cam_bus_ops },
> @@ -98,6 +124,9 @@ static const struct of_device_id gen_pci_of_match[] = {
> { .compatible = "pci-host-ecam-generic",
> .data = &gen_pci_cfg_ecam_bus_ops },
>
> + { .compatible = "cavium,pci-host-thunder-pem",
> + .data = &gen_pci_cfg_thunder_pem_bus_ops },
> +
> { },
> };
> MODULE_DEVICE_TABLE(of, gen_pci_of_match);
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
next prev parent reply other threads:[~2015-09-22 16:05 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-17 22:41 [PATCH 0/3] PCI: Add support for Cavium ThunderX RC and on-SoC devices David Daney
2015-09-17 22:41 ` [PATCH 1/3] PCI: Allow quirks to override SRIOV BARs David Daney
2015-09-17 22:41 ` [PATCH 2/3] PCI: Add quirks for devices found on Cavium ThunderX SoCs David Daney
2015-09-18 7:19 ` Arnd Bergmann
2015-09-18 17:00 ` David Daney
2015-09-18 19:45 ` Arnd Bergmann
2015-09-19 1:00 ` David Daney
2015-09-22 13:19 ` Bjorn Helgaas
2015-09-23 16:24 ` David Daney
2015-09-22 15:39 ` Lorenzo Pieralisi
2015-09-22 19:33 ` Arnd Bergmann
2015-09-17 22:41 ` [PATCH 3/3] PCI: generic: Add support for Cavium ThunderX PCIe root complexes David Daney
2015-09-22 16:05 ` Lorenzo Pieralisi [this message]
2015-09-22 16:13 ` David Daney
2015-09-22 16:40 ` Lorenzo Pieralisi
2015-09-22 16:56 ` David Daney
2015-09-22 18:52 ` Will Deacon
2015-09-22 19:02 ` David Daney
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150922160549.GE17444@red-moon \
--to=lorenzo.pieralisi@arm.com \
--cc=Marc.Zyngier@arm.com \
--cc=Mark.Rutland@arm.com \
--cc=Pawel.Moll@arm.com \
--cc=Will.Deacon@arm.com \
--cc=bhelgaas@google.com \
--cc=david.daney@cavium.com \
--cc=ddaney.cavm@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=galak@codeaurora.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).