From: Bjorn Helgaas <helgaas@kernel.org>
To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: "robh+dt@kernel.org" <robh+dt@kernel.org>,
"pawel.moll@arm.com" <pawel.moll@arm.com>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"ijc+devicetree@hellion.org.uk" <ijc+devicetree@hellion.org.uk>,
"galak@codeaurora.org" <galak@codeaurora.org>,
Michal Simek <michals@xilinx.com>,
Soren Brinkmann <sorenb@xilinx.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"arnd@arndb.de" <arnd@arndb.de>,
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"treding@nvidia.com" <treding@nvidia.com>,
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"Minghuan.Lian@freescale.com" <Minghuan.Lian@freescale.com>,
"m-karicheri2@ti.com" <m-karicheri2@ti.com>,
"hauke@hauke-m.de" <hauke@hauke-m.de>,
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"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Ravikiran Gummaluri <rgummal@xilinx.com>
Subject: Re: [PATCH v5] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
Date: Wed, 28 Oct 2015 07:32:28 -0500 [thread overview]
Message-ID: <20151028123228.GA30510@localhost> (raw)
In-Reply-To: <8520D5D51A55D047800579B0941471980169316D@XAP-PVEXMBX01.xlnx.xilinx.com>
On Wed, Oct 28, 2015 at 10:17:22AM +0000, Bharat Kumar Gogada wrote:
> > On Mon, Oct 26, 2015 at 08:26:26PM +0530, Bharat Kumar Gogada wrote:
> > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> > > +
> > > + while ((status = nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO)) !=
> > 0) {
> > > + for_each_set_bit(bit, &status, 32) {
> > > + nwl_bridge_writel(pcie, 1 << bit,
> > MSGF_MSI_STATUS_LO);
> > > + virq = irq_find_mapping(msi->dev_domain, bit);
> > > + if (virq)
> > > + generic_handle_irq(virq);
> > > + }
> > > + }
> > > +
> > > + chained_irq_exit(chip, desc);
> > > +}
> >
> > These are basically identical. Can you factor them out somehow to avoid
> > repeating the code?
>
> Is it okay if irq_set_chained_handler_and_data being invoked with two different interrupt numbers, but pointing to
> same interrupt handler?
Yes, that should be fine.
> > > +
> > > + pcie->legacy_irq_domain =
> > irq_domain_add_linear(legacy_intc_node, 4,
> > > +
> > &legacy_domain_ops,
> > > + pcie);
> > > +
> > > + if (!pcie->legacy_irq_domain) {
> > > + dev_err(pcie->dev, "failed to create IRQ domain\n");
> > > + return -ENOMEM;
> > > + }
> > > +
> > > +#ifdef CONFIG_PCI_MSI
> > > + msi->dev_domain = irq_domain_add_linear(NULL,
> > INT_PCI_MSI_NR,
> > > + &dev_msi_domain_ops, pcie);
> > > + if (!msi->dev_domain) {
> > > + dev_err(pcie->dev, "failed to create dev IRQ domain\n");
> > > + return -ENOMEM;
> > > + }
> > > + msi->msi_chip.domain = pci_msi_create_irq_domain(node,
> > > +
> > &nwl_msi_domain_info,
> > > + msi->dev_domain);
> > > + if (!msi->msi_chip.domain) {
> > > + dev_err(pcie->dev, "failed to create msi IRQ domain\n");
> > > + irq_domain_remove(msi->dev_domain);
> > > + return -ENOMEM;
> > > + }
> > > +#endif
> > > + return 0;
> > > +}
> > > +
> > > +static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus
> > > +*bus) {
> >
> > It looks strange to have all the "#ifdef CONFIG_PCI_MSI" above, and here
> > we have this long MSI-related function without any ifdefs around it. Seems
> > like this should be ifdef'ed also? What about nwl_pcie_msi_handler_high(),
> > nwl_pcie_msi_handler_low(), nwl_compose_msi_msg(),
> > nwl_msi_set_affinity(), etc.?
> >
> In probe I'm invoking "nwl_pcie_enable_msi" using "if (IS_ENABLED(CONFIG_PCI_MSI)) " check, since this is at run time
> I haven't kept above mentioned functions under #ifdef CONFIG_PCI_MSI.
> The above MSI domain allocation was under ifdef, since if driver was compiled for legacy some of the MSI hierarchy API's and structures aren't available.
OK. It *looks* strange, but maybe it's the best we can do. I'm not
enamored of IS_ENABLED() thing yet; I guess I just haven't
internalized the combination compile-time and run-time behavior.
Bjorn
prev parent reply other threads:[~2015-10-28 12:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-26 14:56 [PATCH v5] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Bharat Kumar Gogada
2015-10-27 19:39 ` Rob Herring
2015-10-27 23:40 ` Bjorn Helgaas
2015-10-28 10:17 ` Bharat Kumar Gogada
2015-10-28 12:32 ` Bjorn Helgaas [this message]
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