From: kbuild test robot <lkp@intel.com>
To: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Cc: kbuild-all@01.org, pratyush.anand@gmail.com,
jingoohan1@gmail.com, gabriele.paoloni@huawei.com,
linuxarm@huawei.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, helgaas@kernel.org
Subject: Re: [PATCH] PCI: Designware: remove wrong RC memory base/limit configuration
Date: Sat, 16 Apr 2016 00:23:33 +0800 [thread overview]
Message-ID: <201604160047.8h0rkLwN%fengguang.wu@intel.com> (raw)
In-Reply-To: <1460737283-117495-1-git-send-email-gabriele.paoloni@huawei.com>
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Hi gabriele,
[auto build test WARNING on pci/next]
[also build test WARNING on v4.6-rc3 next-20160415]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Gabriele-Paoloni/PCI-Designware-remove-wrong-RC-memory-base-limit-configuration/20160416-000746
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-x011-201615 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
drivers/pci/host/pcie-designware.c: In function 'dw_pcie_setup_rc':
>> drivers/pci/host/pcie-designware.c:732:6: warning: unused variable 'memlimit' [-Wunused-variable]
u32 memlimit;
^
>> drivers/pci/host/pcie-designware.c:731:6: warning: unused variable 'membase' [-Wunused-variable]
u32 membase;
^
vim +/memlimit +732 drivers/pci/host/pcie-designware.c
4b1ced84 Jingoo Han 2013-07-31 725 .write = dw_pcie_wr_conf,
340cba60 Jingoo Han 2013-06-21 726 };
340cba60 Jingoo Han 2013-06-21 727
4b1ced84 Jingoo Han 2013-07-31 728 void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60 Jingoo Han 2013-06-21 729 {
340cba60 Jingoo Han 2013-06-21 730 u32 val;
340cba60 Jingoo Han 2013-06-21 @731 u32 membase;
340cba60 Jingoo Han 2013-06-21 @732 u32 memlimit;
340cba60 Jingoo Han 2013-06-21 733
66c5c34b Mohit Kumar 2014-04-14 734 /* set the number of lanes */
f7b7868c Seungwon Jeon 2013-08-28 735 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
:::::: The code at line 732 was first introduced by commit
:::::: 340cba6092c2c1688629d327b74e7eb746a571a7 pci: Add PCIe driver for Samsung Exynos
:::::: TO: Jingoo Han <jg1.han@samsung.com>
:::::: CC: Arnd Bergmann <arnd@arndb.de>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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next prev parent reply other threads:[~2016-04-15 16:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-15 16:21 [PATCH] PCI: Designware: remove wrong RC memory base/limit configuration Gabriele Paoloni
2016-04-15 16:23 ` kbuild test robot [this message]
2016-04-16 11:05 ` Gabriele Paoloni
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