From: Bjorn Helgaas <helgaas@kernel.org>
To: Jisheng Zhang <jszhang@marvell.com>
Cc: jingoohan1@gmail.com, pratyush.anand@gmail.com,
bhelgaas@google.com, Joao.Pinto@synopsys.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
Date: Wed, 17 Aug 2016 16:01:00 -0500 [thread overview]
Message-ID: <20160817210100.GD27353@localhost> (raw)
In-Reply-To: <1470823623-1360-1-git-send-email-jszhang@marvell.com>
On Wed, Aug 10, 2016 at 06:07:01PM +0800, Jisheng Zhang wrote:
> patch1 is a trivial clean up: move the parameters for wait for link
> into the core pcie-designware.c
>
> Since link may be UP but still in link training, if so, we can't think
> the link is up and operating correctly. So patch2 teaches
> dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
>
> Since v1:
> - add Joao's Ack
> - rebased on v4.8-rc1
>
> Jisheng Zhang (2):
> PCI: designware: mv parameters for wait for link into
> pcie-designware.c
> PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
>
> drivers/pci/host/pcie-designware.c | 11 +++++++++--
> drivers/pci/host/pcie-designware.h | 5 -----
> 2 files changed, 9 insertions(+), 7 deletions(-)
Applied to pci/host-designware for v4.9, thanks, Jisheng.
next prev parent reply other threads:[~2016-08-17 21:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-10 10:07 [PATCH v2 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
2016-08-10 10:07 ` [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c Jisheng Zhang
2016-08-10 10:07 ` [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
2016-08-10 10:21 ` [PATCH v2 0/2] " Jisheng Zhang
2016-08-17 21:01 ` Bjorn Helgaas [this message]
-- strict thread matches above, loose matches on Subject: below --
2016-08-10 5:31 Jisheng Zhang
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