[PATCH 1/2] PCI: rockchip: fix broken ASPM due to incorrect L1PwrOnSc/Val

[PATCH 1/2] PCI: rockchip: fix broken ASPM due to incorrect L1PwrOnSc/Val

[Shawn Lin]

This is a bug of controller found recently which makes the
default values of L1PwrOnSc and L1PwrOnVal unreliable when
enabling ASPM. We could work around this by reading L1 substate
control 2 register and then write back the value again.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

 drivers/pci/host/pcie-rockchip.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 1671d02..ed782b51 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -40,6 +40,7 @@
 #define PCIE_CLIENT_BASE			0x0
 #define PCIE_RC_CONFIG_NORMAL_BASE		0x800000
 #define PCIE_RC_CONFIG_BASE			0xa00000
+#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2	0x90c
 #define PCIE_RC_CONFIG_LCSR			0xd0
 #define  PCIE_RC_CONFIG_LCSR_LBMIE		BIT(10)
 #define  PCIE_RC_CONFIG_LCSR_LABIE		BIT(11)
@@ -477,6 +478,18 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 		return err;
 	}
 
+	/*
+	 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2
+	 * before enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
+	 * reliable which makes the controller in broken state when
+	 * enabling ASPM. This is a controller's bug we need to work
+	 * around.
+	 */
+	status = pcie_read(port,  PCIE_RC_CONFIG_BASE +
+				  PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
+	pcie_write(port, status,  PCIE_RC_CONFIG_BASE +
+				  PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
+
 	/* Enable Gen1 training */
 	pcie_write(port,
 		   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
-- 
2.3.7

[PATCH 2/2] MAINTAINERS: Add rockchip pcie driver entry

[Shawn Lin]

The pcie driver of Rockchip has no entry in the MAINTAINERS
file, so add one.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 20bb1d0..c0e623f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9083,6 +9083,15 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F:	drivers/pci/host/pcie-hisi.c
 
+PCIE DRIVER FOR ROCKCHIP
+M:	Shawn Lin <shawn.lin@rock-chips.com>
+M:	Wenrui Li <wenrui.li@rock-chips.com>
+L:	linux-pci@vger.kernel.org
+L:	linux-rockchip@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+F:	drivers/pci/host/pcie-rockchip.c
+
 PCIE DRIVER FOR QUALCOMM MSM
 M:     Stanimir Varbanov <svarbanov@mm-sol.com>
 L:     linux-pci@vger.kernel.org
-- 
2.3.7

Re: [PATCH 1/2] PCI: rockchip: fix broken ASPM due to incorrect L1PwrOnSc/Val

[Bjorn Helgaas]

On Thu, Aug 25, 2016 at 04:03:34PM +0800, Shawn Lin wrote:
> This is a bug of controller found recently which makes the
> default values of L1PwrOnSc and L1PwrOnVal unreliable when
> enabling ASPM. We could work around this by reading L1 substate
> control 2 register and then write back the value again.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

My pci/host-rockchip branch hasn't been merged anywhere, so I just folded
both these patches into the original commits.

> ---
> 
>  drivers/pci/host/pcie-rockchip.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 1671d02..ed782b51 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -40,6 +40,7 @@
>  #define PCIE_CLIENT_BASE			0x0
>  #define PCIE_RC_CONFIG_NORMAL_BASE		0x800000
>  #define PCIE_RC_CONFIG_BASE			0xa00000
> +#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2	0x90c
>  #define PCIE_RC_CONFIG_LCSR			0xd0
>  #define  PCIE_RC_CONFIG_LCSR_LBMIE		BIT(10)
>  #define  PCIE_RC_CONFIG_LCSR_LABIE		BIT(11)
> @@ -477,6 +478,18 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
>  		return err;
>  	}
>  
> +	/*
> +	 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2
> +	 * before enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
> +	 * reliable which makes the controller in broken state when
> +	 * enabling ASPM. This is a controller's bug we need to work
> +	 * around.
> +	 */
> +	status = pcie_read(port,  PCIE_RC_CONFIG_BASE +
> +				  PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> +	pcie_write(port, status,  PCIE_RC_CONFIG_BASE +
> +				  PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> +
>  	/* Enable Gen1 training */
>  	pcie_write(port,
>  		   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
> -- 
> 2.3.7
> 
>