From: Guenter Roeck <linux@roeck-us.net>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>,
devicetree@vger.kernel.org, Wenrui Li <wenrui.li@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de>,
Marc Zyngier <marc.zyngier@arm.com>,
linux-pci@vger.kernel.org,
Brian Norris <briannorris@chromium.org>,
linux-kernel@vger.kernel.org,
Doug Anderson <dianders@chromium.org>,
linux-rockchip@lists.infradead.org,
Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v2 07/15] Simplify the confusing HIWORD_UPDATE scheme.
Date: Fri, 2 Sep 2016 14:38:06 -0700 [thread overview]
Message-ID: <20160902213806.GA31011@roeck-us.net> (raw)
In-Reply-To: <20160902155453.8650.29613.stgit@bhelgaas-glaptop2.roam.corp.google.com>
On Fri, Sep 02, 2016 at 10:54:53AM -0500, Bjorn Helgaas wrote:
>
> ---
> drivers/pci/host/pcie-rockchip.c | 70 +++++++++++++-------------------------
> 1 file changed, 24 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index c0c3ad5..b204567 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -115,36 +115,26 @@
> (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
> PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
>
> -/*
> - * The higher 16-bit of this register is used for write protection
> - * only if BIT(x + 16) set to 1 the BIT(x) can be written.
> - */
> -#define HIWORD_UPDATE(val, mask, shift) \
> - ((val) << (shift) | (mask) << ((shift) + 16))
> -
> #define RC_REGION_0_ADDR_TRANS_H 0x00000000
> #define RC_REGION_0_ADDR_TRANS_L 0x00000000
> #define RC_REGION_0_PASS_BITS (25 - 1)
> #define MAX_AXI_WRAPPER_REGION_NUM 33
> #define PCIE_CORE_LCSR_RETRAIN_LINK BIT(5)
> -#define PCIE_CLIENT_CONF_ENABLE BIT(0)
> -#define PCIE_CLIENT_CONF_ENABLE_SHIFT 0
> -#define PCIE_CLIENT_CONF_ENABLE_MASK 0x1
> -#define PCIE_CLIENT_LINK_TRAIN_ENABLE 1
> -#define PCIE_CLIENT_LINK_TRAIN_SHIFT 1
> -#define PCIE_CLIENT_LINK_TRAIN_MASK 0x1
> -#define PCIE_CLIENT_ARI_ENABLE BIT(0)
> -#define PCIE_CLIENT_ARI_ENABLE_SHIFT 3
> -#define PCIE_CLIENT_ARI_ENABLE_MASK 0x1
> -#define PCIE_CLIENT_CONF_LANE_NUM(x) (x / 2)
> -#define PCIE_CLIENT_CONF_LANE_NUM_SHIFT 4
> -#define PCIE_CLIENT_CONF_LANE_NUM_MASK 0x3
> -#define PCIE_CLIENT_MODE_RC BIT(0)
> -#define PCIE_CLIENT_MODE_SHIFT 6
> -#define PCIE_CLIENT_MODE_MASK 0x1
> -#define PCIE_CLIENT_GEN_SEL_2 1
> -#define PCIE_CLIENT_GEN_SEL_SHIFT 7
> -#define PCIE_CLIENT_GEN_SEL_MASK 0x1
> +
> +/*
> + * The upper 16 bits of the PCIE_CLIENT registers are a write mask for the
> + * lower 16 bits. This allows atomic updates of the register without
> + * locking.
> + */
> +#define HIWORD_UPDATE(mask, val) ((mask << 16) | val)
> +
> +#define ENCODE_LANES(x) (((x >> 1) & 3) << 4)
(x) ?
> +
> +#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE(0x0001, 0x0001)
> +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE(0x0002, 0x0002)
> +#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
> +#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE(0x0040, 0x0040)
> +
> #define PCIE_CLIENT_LINK_STATUS_UP 0x3
> #define PCIE_CLIENT_LINK_STATUS_SHIFT 20
> #define PCIE_CLIENT_LINK_STATUS_MASK 0x3
> @@ -423,22 +413,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> }
>
> rockchip_pcie_write(rockchip,
> - HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
> - PCIE_CLIENT_CONF_ENABLE_MASK,
> - PCIE_CLIENT_CONF_ENABLE_SHIFT) |
> - HIWORD_UPDATE(PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes),
> - PCIE_CLIENT_CONF_LANE_NUM_MASK,
> - PCIE_CLIENT_CONF_LANE_NUM_SHIFT) |
> - HIWORD_UPDATE(PCIE_CLIENT_MODE_RC,
> - PCIE_CLIENT_MODE_MASK,
> - PCIE_CLIENT_MODE_SHIFT) |
> - HIWORD_UPDATE(PCIE_CLIENT_ARI_ENABLE,
> - PCIE_CLIENT_ARI_ENABLE_MASK,
> - PCIE_CLIENT_ARI_ENABLE_SHIFT) |
> - HIWORD_UPDATE(PCIE_CLIENT_GEN_SEL_2,
> - PCIE_CLIENT_GEN_SEL_MASK,
> - PCIE_CLIENT_GEN_SEL_SHIFT),
> - PCIE_CLIENT_BASE);
> + PCIE_CLIENT_CONF_ENABLE |
> + PCIE_CLIENT_LINK_TRAIN_ENABLE |
> + PCIE_CLIENT_ARI_ENABLE |
> + PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
> + PCIE_CLIENT_MODE_RC |
> + PCIE_CLIENT_GEN_SEL_2,
> + PCIE_CLIENT_BASE);
>
This is soooo much better ...
Guenter
> err = phy_power_on(rockchip->phy);
> if (err) {
> @@ -482,11 +463,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
>
> /* Enable Gen1 training */
> - rockchip_pcie_write(rockchip,
> - HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
> - PCIE_CLIENT_LINK_TRAIN_MASK,
> - PCIE_CLIENT_LINK_TRAIN_SHIFT),
> - PCIE_CLIENT_BASE);
> + rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> + PCIE_CLIENT_BASE);
>
> gpiod_set_value(rockchip->ep_gpio, 1);
>
>
next prev parent reply other threads:[~2016-09-02 21:38 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-02 15:53 [PATCH v2 00/15] PCI: rockchip: Cleanups against v10 Bjorn Helgaas
2016-09-02 15:53 ` [PATCH v2 01/15] Remove unused symbols, unnecessary parens, other minor comments from Bjorn Helgaas
2016-09-02 21:42 ` Guenter Roeck
2016-09-02 22:15 ` Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 02/15] Rename pcie_read() and pcie_write() to rockchip_pcie_read() and Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 03/15] Always use "rockchip" as the pointer to per-device struct Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 04/15] Rename struct rockchip_pcie_port to struct rockchip_pcie Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 05/15] Use a local "dev" to avoid repetition of "rockchip->dev" Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 06/15] Add comment about why 32-bit read/modify/write isn't safe Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 07/15] Simplify the confusing HIWORD_UPDATE scheme Bjorn Helgaas
2016-09-02 21:38 ` Guenter Roeck [this message]
2016-09-02 22:09 ` Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 08/15] Remove duplicate CSR definition Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 09/15] Move CSR bases into definition Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 10/15] Group related CSR definitions together Bjorn Helgaas
2016-09-02 21:40 ` Guenter Roeck
2016-09-02 15:55 ` [PATCH v2 11/15] Rename PCIE_CORE_RC_CONF_SCC_SHIFT to match similar definitions Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 12/15] Rename ROCKCHIP_PCIE_RPIFR1_INTR_MASK and ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 13/15] The register at PCIE_CLIENT_BASE presumably has a name of its own. Add a Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 14/15] Simplify testing of link status and speed testing Bjorn Helgaas
2016-09-02 15:56 ` [PATCH v2 15/15] Move msleeps to address Guenter's comments Bjorn Helgaas
2016-09-03 2:37 ` [PATCH v2 00/15] PCI: rockchip: Cleanups against v10 Shawn Lin
2016-09-03 16:34 ` Bjorn Helgaas
2016-09-03 17:17 ` Bjorn Helgaas
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