From: Graeme Gregory <gg@slimlogic.co.uk>
To: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Cc: Tomasz Nowicki <tn@semihalf.com>,
"liudongdong (C)" <liudongdong3@huawei.com>,
"helgaas@kernel.org" <helgaas@kernel.org>,
"arnd@arndb.de" <arnd@arndb.de>,
"rafael@kernel.org" <rafael@kernel.org>,
"Lorenzo.Pieralisi@arm.com" <Lorenzo.Pieralisi@arm.com>,
"Wangzhou (B)" <wangzhou1@hisilicon.com>,
"pratyush.anand@gmail.com" <pratyush.anand@gmail.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"jcm@redhat.com" <jcm@redhat.com>,
"Chenxin (Charles)" <charles.chenxin@huawei.com>,
"hanjun.guo@linaro.org" <hanjun.guo@linaro.org>,
Linuxarm <linuxarm@huawei.com>
Subject: Re: [PATCH V6 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers
Date: Wed, 23 Nov 2016 09:44:28 +0000 [thread overview]
Message-ID: <20161123094428.GA878@linaro-xps13.localdomain> (raw)
In-Reply-To: <EE11001F9E5DDD47B7634E2F8A612F2E1F92CA85@lhreml507-mbx>
On Tue, Nov 22, 2016 at 03:05:29PM +0000, Gabriele Paoloni wrote:
> Hi Tomasz
>
> > -----Original Message-----
> > From: Tomasz Nowicki [mailto:tn@semihalf.com]
> > Sent: 22 November 2016 13:58
> > To: liudongdong (C); helgaas@kernel.org; arnd@arndb.de;
> > rafael@kernel.org; Lorenzo.Pieralisi@arm.com; Wangzhou (B);
> > pratyush.anand@gmail.com
> > Cc: linux-pci@vger.kernel.org; linux-acpi@vger.kernel.org; linux-
> > kernel@vger.kernel.org; jcm@redhat.com; Gabriele Paoloni; Chenxin
> > (Charles); hanjun.guo@linaro.org; Linuxarm
> > Subject: Re: [PATCH V6 2/2] PCI/ACPI: hisi: Add ACPI support for
> > HiSilicon SoCs Host Controllers
> >
> > On 22.11.2016 13:08, Dongdong Liu wrote:
> > > PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
> > > It is non ECAM only for the RC bus config space;for any other bus
> > > underneath the root bus we support ECAM access.
> > > Add specific quirks for PCI config space accessors.This involves:
> > > 1. New initialization call hisi_pcie_init() to obtain rc base
> > > addresses from PNP0C02 at the root of the ACPI namespace (under
> > \_SB).
> > > 2. New entry in common quirk array.
> > >
> > > Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
> > > Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
> > > ---
> > > MAINTAINERS | 1 +
> > > drivers/acpi/pci_mcfg.c | 13 +++++
> > > drivers/pci/host/Kconfig | 7 +++
> > > drivers/pci/host/Makefile | 1 +
> > > drivers/pci/host/pcie-hisi-acpi.c | 119
> > ++++++++++++++++++++++++++++++++++++++
> > > include/linux/pci-ecam.h | 5 ++
> > > 6 files changed, 146 insertions(+)
> > > create mode 100644 drivers/pci/host/pcie-hisi-acpi.c
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 1cd38a7..b224caa 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -9358,6 +9358,7 @@ L: linux-pci@vger.kernel.org
> > > S: Maintained
> > > F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> > > F: drivers/pci/host/pcie-hisi.c
> > > +F: drivers/pci/host/pcie-hisi-acpi.c
> > >
> > > PCIE DRIVER FOR ROCKCHIP
> > > M: Shawn Lin <shawn.lin@rock-chips.com>
> > > diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> > > index ac21db3..3297c5a 100644
> > > --- a/drivers/acpi/pci_mcfg.c
> > > +++ b/drivers/acpi/pci_mcfg.c
> > > @@ -57,6 +57,19 @@ struct mcfg_fixup {
> > > { "QCOM ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, &pci_32b_ops },
> > > { "QCOM ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, &pci_32b_ops },
> > > { "QCOM ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, &pci_32b_ops },
> > > +#ifdef CONFIG_PCI_ECAM_QUIRKS
> > > + #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
> > > + { "HISI ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
> > > + { "HISI ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
> > > + { "HISI ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
> > > + { "HISI ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
> > > + PCI_ACPI_QUIRK_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
> > > + PCI_ACPI_QUIRK_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
> > > + PCI_ACPI_QUIRK_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
> > > + PCI_ACPI_QUIRK_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
> > > + PCI_ACPI_QUIRK_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
> > > + PCI_ACPI_QUIRK_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
> > > +#endif
> > > };
> > >
> > > static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
> > > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> > > index ae98644..1fbade5 100644
> > > --- a/drivers/pci/host/Kconfig
> > > +++ b/drivers/pci/host/Kconfig
> > > @@ -301,4 +301,11 @@ config VMD
> > > To compile this driver as a module, choose M here: the
> > > module will be called vmd.
> > >
> > > +config PCI_ECAM_QUIRKS
> > > + bool "PCI ECAM quirks for ARM64 platform"
> > > + depends on PCI_ECAM && ARM64 && ACPI
> > > + help
> > > + Say y here to enable your platform-specific config access that
> > > + is not ECAM compliant.
> > > +
> >
> > ARM64 selects PCI_ECAM for ACPI anyway so we can skip it here.
>
> Yes sure
>
> >
> > How about selecting PCI_ECAM_QUIRKS from ARM64 Kconfig:
>
> I don't think we should assume that ARM64 platforms should
> support quirks by default...
> i.e. from my perspective the quirk module should go in only
> if strictly required by the platform you're working on.
>
> Thoughts?
>
> Thanks
>
No, same kernel multiple machines is the model, code should go in
unconditional.
Graeme
next prev parent reply other threads:[~2016-11-23 9:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-22 12:08 [PATCH V6 0/2] Add ACPI support for HiSilicon SoCs Host Controllers Dongdong Liu
2016-11-22 12:08 ` [PATCH V6 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform Dongdong Liu
2016-11-22 12:32 ` Tomasz Nowicki
2016-11-23 1:44 ` Dongdong Liu
2016-11-23 2:24 ` Dongdong Liu
2016-11-22 15:56 ` Lorenzo Pieralisi
2016-11-22 16:09 ` Gabriele Paoloni
2016-11-22 17:03 ` Lorenzo Pieralisi
2016-11-22 12:08 ` [PATCH V6 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers Dongdong Liu
2016-11-22 13:58 ` Tomasz Nowicki
2016-11-22 15:05 ` Gabriele Paoloni
2016-11-23 9:44 ` Graeme Gregory [this message]
2016-11-23 14:02 ` Gabriele Paoloni
2016-12-22 8:31 ` [PATCH V6 0/2] " Ming Lei
2016-12-22 12:30 ` Dongdong Liu
2016-12-22 12:40 ` Ming Lei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20161123094428.GA878@linaro-xps13.localdomain \
--to=gg@slimlogic.co.uk \
--cc=Lorenzo.Pieralisi@arm.com \
--cc=arnd@arndb.de \
--cc=charles.chenxin@huawei.com \
--cc=gabriele.paoloni@huawei.com \
--cc=hanjun.guo@linaro.org \
--cc=helgaas@kernel.org \
--cc=jcm@redhat.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linuxarm@huawei.com \
--cc=liudongdong3@huawei.com \
--cc=pratyush.anand@gmail.com \
--cc=rafael@kernel.org \
--cc=tn@semihalf.com \
--cc=wangzhou1@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).