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Subject: Re: Disabling msix interrupts
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From: David Laight <David.Laight@ACULAB.COM>
Date: Mon, 6 Feb 2017 17:23:54 +0000

> Although the 'store buffer' on the sparc cpus I used to use would
> let reads overtake writes. So you did have to read back the address
> of the last write - not sure about modern sparc cpus.

Never would any sparc cpu do so when any of the operations involved
were to "side effect" locations, as PCI config space is.