* [PATCH v3 0/3] i.MX7 PCI support
@ 2017-02-06 15:17 Andrey Smirnov
2017-02-06 15:17 ` [PATCH v3 1/3] PCI: imx6: Fix a typo in error message Andrey Smirnov
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Andrey Smirnov @ 2017-02-06 15:17 UTC (permalink / raw)
To: linux-pci
Cc: Andrey Smirnov, yurovsky, Lucas Stach, Fabio Estevam,
Bjorn Helgaas, linux-arm-kernel, linux-kernel
Hello, everyone:
This is a third iteration of the code that adds PCI-subsystem bits
necessary for enabling PCI support on i.MX7.
Changes since v2 (can be found at [version2]):
- Collected Reviewed-by for patch #2 from Lucas
- Reset logic implementation moved out into a reset controller
driver (see [reset1])
- Removed unused leftover code
Changes since v1 (can be found at [version1]):
- All GPC related code moved into a separate driver (see [gpc1])
- Removed GPIO probe deferral logging
- Fixed section mismatch warning
- Minor reformatting of fsl,imx6q-pcie.txt(as per Rob
Herring's request)
[version2] https://lkml.org/lkml/2017/2/1/510
[version1] https://lkml.org/lkml/2017/1/19/488
[gpc1] https://lkml.org/lkml/2017/2/6/551
[reset1] https://lkml.org/lkml/2017/2/6/554
Andrey Smirnov (3):
PCI: imx6: Fix a typo in error message
PCI: imx6: Allow probe deferal by reset GPIO
PCI: imx6: Add code to support i.MX7D
.../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 +-
drivers/pci/host/pci-imx6.c | 131 ++++++++++++++++-----
include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 4 +
3 files changed, 111 insertions(+), 30 deletions(-)
--
2.9.3
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 1/3] PCI: imx6: Fix a typo in error message 2017-02-06 15:17 [PATCH v3 0/3] i.MX7 PCI support Andrey Smirnov @ 2017-02-06 15:17 ` Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 2/3] PCI: imx6: Allow probe deferal by reset GPIO Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 3/3] PCI: imx6: Add code to support i.MX7D Andrey Smirnov 2 siblings, 0 replies; 6+ messages in thread From: Andrey Smirnov @ 2017-02-06 15:17 UTC (permalink / raw) To: linux-pci Cc: Andrey Smirnov, linux-kernel, Fabio Estevam, Bjorn Helgaas, yurovsky, linux-arm-kernel, Lucas Stach Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> --- drivers/pci/host/pci-imx6.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index c8cefb0..50a1291 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -678,8 +678,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, "pcie_inbound_axi"); if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { - dev_err(dev, - "pcie_incbound_axi clock missing or invalid\n"); + dev_err(dev, "pcie_inbound_axi clock missing or invalid\n"); return PTR_ERR(imx6_pcie->pcie_inbound_axi); } } -- 2.9.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/3] PCI: imx6: Allow probe deferal by reset GPIO 2017-02-06 15:17 [PATCH v3 0/3] i.MX7 PCI support Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 1/3] PCI: imx6: Fix a typo in error message Andrey Smirnov @ 2017-02-06 15:17 ` Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 3/3] PCI: imx6: Add code to support i.MX7D Andrey Smirnov 2 siblings, 0 replies; 6+ messages in thread From: Andrey Smirnov @ 2017-02-06 15:17 UTC (permalink / raw) To: linux-pci Cc: Andrey Smirnov, yurovsky, Lucas Stach, Bjorn Helgaas, Fabio Estevam, linux-arm-kernel, linux-kernel Some designs implement reset GPIO via a GPIO expander connected to a peripheral bus. One such example would be i.MX7 Sabre board where said GPIO is provided by SPI shift register connected to a bitbanged SPI bus. In order to support such designs allow reset GPIO request to defer probing of the driver. Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> --- drivers/pci/host/pci-imx6.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 50a1291..3ef8093 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -611,7 +611,7 @@ static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, return 0; } -static int __init imx6_pcie_probe(struct platform_device *pdev) +static int imx6_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct imx6_pcie *imx6_pcie; @@ -653,6 +653,8 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) dev_err(dev, "unable to get reset gpio\n"); return ret; } + } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { + return imx6_pcie->reset_gpio; } /* Fetch clocks */ @@ -746,11 +748,12 @@ static struct platform_driver imx6_pcie_driver = { .name = "imx6q-pcie", .of_match_table = imx6_pcie_of_match, }, + .probe = imx6_pcie_probe, .shutdown = imx6_pcie_shutdown, }; static int __init imx6_pcie_init(void) { - return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); + return platform_driver_register(&imx6_pcie_driver); } device_initcall(imx6_pcie_init); -- 2.9.3 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/3] PCI: imx6: Add code to support i.MX7D 2017-02-06 15:17 [PATCH v3 0/3] i.MX7 PCI support Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 1/3] PCI: imx6: Fix a typo in error message Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 2/3] PCI: imx6: Allow probe deferal by reset GPIO Andrey Smirnov @ 2017-02-06 15:17 ` Andrey Smirnov 2017-02-06 15:33 ` Lucas Stach 2 siblings, 1 reply; 6+ messages in thread From: Andrey Smirnov @ 2017-02-06 15:17 UTC (permalink / raw) To: linux-pci Cc: Andrey Smirnov, yurovsky, Lucas Stach, Bjorn Helgaas, Fabio Estevam, Rob Herring, Mark Rutland, Lee Jones, linux-arm-kernel, devicetree, linux-kernel Add various bits of code needed to support i.MX7D variant of the IP. Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Lee Jones <lee.jones@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> --- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 +- drivers/pci/host/pci-imx6.c | 121 ++++++++++++++++----- include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 4 + 3 files changed, 105 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 83aeb1f..9f57759 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -4,7 +4,11 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie" +- compatible: + - "fsl,imx6q-pcie" + - "fsl,imx6sx-pcie", + - "fsl,imx6qp-pcie" + - "fsl,imx7d-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 3ef8093..34a21c9 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -17,6 +17,7 @@ #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/mfd/syscon/imx7-iomuxc-gpr.h> #include <linux/module.h> #include <linux/of_gpio.h> #include <linux/of_device.h> @@ -27,6 +28,7 @@ #include <linux/signal.h> #include <linux/types.h> #include <linux/interrupt.h> +#include <linux/reset.h> #include "pcie-designware.h" @@ -36,6 +38,7 @@ enum imx6_pcie_variants { IMX6Q, IMX6SX, IMX6QP, + IMX7D, }; struct imx6_pcie { @@ -47,6 +50,8 @@ struct imx6_pcie { struct clk *pcie_inbound_axi; struct clk *pcie; struct regmap *iomuxc_gpr; + struct reset_control *pciephy_reset; + struct reset_control *apps_reset; enum imx6_pcie_variants variant; u32 tx_deemph_gen1; u32 tx_deemph_gen2_3p5db; @@ -56,6 +61,11 @@ struct imx6_pcie { int link_gen; }; +/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ +#define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000 +#define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50 +#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 + /* PCIe Root Complex registers (memory-mapped) */ #define PCIE_RC_LCR 0x7c #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 @@ -251,6 +261,9 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) u32 val, gpr1, gpr12; switch (imx6_pcie->variant) { + case IMX7D: + reset_control_assert(imx6_pcie->pciephy_reset); + break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -333,11 +346,33 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); break; + case IMX7D: + break; } return ret; } +static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) +{ + u32 val; + unsigned int retries; + struct pcie_port *pp = &imx6_pcie->pp; + struct device *dev = pp->dev; + + for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) { + regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val); + + if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED) + return; + + usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN, + PHY_PLL_LOCK_WAIT_USLEEP_MAX); + } + + dev_err(dev, "PCIe PLL lock timeout\n"); +} + static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct pcie_port *pp = &imx6_pcie->pp; @@ -381,6 +416,11 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } switch (imx6_pcie->variant) { + case IMX7D: + reset_control_assert(imx6_pcie->apps_reset); + reset_control_deassert(imx6_pcie->pciephy_reset); + imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); + break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); @@ -407,35 +447,44 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { - if (imx6_pcie->variant == IMX6SX) + switch (imx6_pcie->variant) { + case IMX7D: + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); + break; + case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); + /* FALLTHROUGH */ + default: + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); + /* configure constant input signal to the pcie ctrl and phy */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6Q_GPR12_LOS_LEVEL, 9 << 4); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN1, + imx6_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, + imx6_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, + imx6_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_FULL, + imx6_pcie->tx_swing_full << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + IMX6Q_GPR8_TX_SWING_LOW, + imx6_pcie->tx_swing_low << 25); + break; + } - /* configure constant input signal to the pcie ctrl and phy */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_LOS_LEVEL, 9 << 4); - - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN1, - imx6_pcie->tx_deemph_gen1 << 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, - imx6_pcie->tx_deemph_gen2_3p5db << 6); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, - imx6_pcie->tx_deemph_gen2_6db << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_FULL, - imx6_pcie->tx_swing_full << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, - IMX6Q_GPR8_TX_SWING_LOW, - imx6_pcie->tx_swing_low << 25); } static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) @@ -498,8 +547,11 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp); /* Start LTSSM. */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); + if (imx6_pcie->variant == IMX7D) + reset_control_deassert(imx6_pcie->apps_reset); + else + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); ret = imx6_pcie_wait_for_link(imx6_pcie); if (ret) { @@ -676,13 +728,31 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(imx6_pcie->pcie); } - if (imx6_pcie->variant == IMX6SX) { + switch (imx6_pcie->variant) { + case IMX6SX: imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, "pcie_inbound_axi"); if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { dev_err(dev, "pcie_inbound_axi clock missing or invalid\n"); return PTR_ERR(imx6_pcie->pcie_inbound_axi); } + break; + case IMX7D: + imx6_pcie->pciephy_reset = devm_reset_control_get(dev, + "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) { + dev_err(dev, "Failed to get PCIEPHY reset contol\n"); + return PTR_ERR(imx6_pcie->pciephy_reset); + } + + imx6_pcie->apps_reset = devm_reset_control_get(dev, "apps"); + if (IS_ERR(imx6_pcie->apps_reset)) { + dev_err(dev, "Failed to get PCIE APPS reset contol\n"); + return PTR_ERR(imx6_pcie->apps_reset); + } + break; + default: + break; } /* Grab GPR config register range */ @@ -740,6 +810,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, }, { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, }, { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, }, + { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, }, {}, }; diff --git a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h index 4585d61..abbd524 100644 --- a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h @@ -44,4 +44,8 @@ #define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4) +#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5) + +#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31) + #endif /* __LINUX_IMX7_IOMUXC_GPR_H */ -- 2.9.3 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 3/3] PCI: imx6: Add code to support i.MX7D 2017-02-06 15:17 ` [PATCH v3 3/3] PCI: imx6: Add code to support i.MX7D Andrey Smirnov @ 2017-02-06 15:33 ` Lucas Stach 2017-02-06 19:18 ` Andrey Smirnov 0 siblings, 1 reply; 6+ messages in thread From: Lucas Stach @ 2017-02-06 15:33 UTC (permalink / raw) To: Andrey Smirnov Cc: Mark Rutland, devicetree, linux-pci, linux-kernel, Fabio Estevam, Rob Herring, Bjorn Helgaas, Lee Jones, linux-arm-kernel, yurovsky Am Montag, den 06.02.2017, 07:17 -0800 schrieb Andrey Smirnov: > Add various bits of code needed to support i.MX7D variant of the IP. > > Cc: yurovsky@gmail.com > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Bjorn Helgaas <bhelgaas@google.com> > Cc: Fabio Estevam <fabio.estevam@nxp.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Lee Jones <lee.jones@linaro.org> > Cc: linux-arm-kernel@lists.infradead.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Two small comments inline, otherwise looks real good now. > --- > .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 +- > drivers/pci/host/pci-imx6.c | 121 ++++++++++++++++----- > include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 4 + > 3 files changed, 105 insertions(+), 26 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > index 83aeb1f..9f57759 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > @@ -4,7 +4,11 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP > and thus inherits all the common properties defined in designware-pcie.txt. > > Required properties: > -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie" > +- compatible: > + - "fsl,imx6q-pcie" > + - "fsl,imx6sx-pcie", > + - "fsl,imx6qp-pcie" > + - "fsl,imx7d-pcie" > - reg: base address and length of the PCIe controller > - interrupts: A list of interrupt outputs of the controller. Must contain an > entry for each entry in the interrupt-names property. This misses an "Additional required properties for imx7d-pcie" section listing the required reset handles. > diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c > index 3ef8093..34a21c9 100644 > --- a/drivers/pci/host/pci-imx6.c > +++ b/drivers/pci/host/pci-imx6.c [...] > static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) > { > struct pcie_port *pp = &imx6_pcie->pp; > @@ -381,6 +416,11 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) > } > > switch (imx6_pcie->variant) { > + case IMX7D: > + reset_control_assert(imx6_pcie->apps_reset); Can this reset assertion be moved into imx6_pcie_assert_core_reset()? This may change the programming order slightly from the downstream driver, but I guess that won't hurt if this is the equivalent of the LTSSM enable signal. Regards, Lucas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 3/3] PCI: imx6: Add code to support i.MX7D 2017-02-06 15:33 ` Lucas Stach @ 2017-02-06 19:18 ` Andrey Smirnov 0 siblings, 0 replies; 6+ messages in thread From: Andrey Smirnov @ 2017-02-06 19:18 UTC (permalink / raw) To: Lucas Stach Cc: Mark Rutland, devicetree, linux-pci, linux-kernel, Fabio Estevam, Rob Herring, Bjorn Helgaas, Lee Jones, linux-arm-kernel, Andrey Yurovsky On Mon, Feb 6, 2017 at 7:33 AM, Lucas Stach <l.stach@pengutronix.de> wrote: > Am Montag, den 06.02.2017, 07:17 -0800 schrieb Andrey Smirnov: >> Add various bits of code needed to support i.MX7D variant of the IP. >> >> Cc: yurovsky@gmail.com >> Cc: Lucas Stach <l.stach@pengutronix.de> >> Cc: Bjorn Helgaas <bhelgaas@google.com> >> Cc: Fabio Estevam <fabio.estevam@nxp.com> >> Cc: Rob Herring <robh+dt@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Lee Jones <lee.jones@linaro.org> >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: devicetree@vger.kernel.org >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> > > Two small comments inline, otherwise looks real good now. > >> --- >> .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 +- >> drivers/pci/host/pci-imx6.c | 121 ++++++++++++++++----- >> include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 4 + >> 3 files changed, 105 insertions(+), 26 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt >> index 83aeb1f..9f57759 100644 >> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt >> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt >> @@ -4,7 +4,11 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP >> and thus inherits all the common properties defined in designware-pcie.txt. >> >> Required properties: >> -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie" >> +- compatible: >> + - "fsl,imx6q-pcie" >> + - "fsl,imx6sx-pcie", >> + - "fsl,imx6qp-pcie" >> + - "fsl,imx7d-pcie" >> - reg: base address and length of the PCIe controller >> - interrupts: A list of interrupt outputs of the controller. Must contain an >> entry for each entry in the interrupt-names property. > > This misses an "Additional required properties for imx7d-pcie" section > listing the required reset handles. Darn! Forgot to update this part. Will fix in v4. > >> diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c >> index 3ef8093..34a21c9 100644 >> --- a/drivers/pci/host/pci-imx6.c >> +++ b/drivers/pci/host/pci-imx6.c > > [...] > >> static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) >> { >> struct pcie_port *pp = &imx6_pcie->pp; >> @@ -381,6 +416,11 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) >> } >> >> switch (imx6_pcie->variant) { >> + case IMX7D: >> + reset_control_assert(imx6_pcie->apps_reset); > > Can this reset assertion be moved into imx6_pcie_assert_core_reset()? > This may change the programming order slightly from the downstream > driver, but I guess that won't hurt if this is the equivalent of the > LTSSM enable signal. I don't see why it wouldn't be possible to move it. I'll give it a try on a real HW and update v4 accordingly. Thanks, Andrey Smirnov _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-02-06 19:18 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-02-06 15:17 [PATCH v3 0/3] i.MX7 PCI support Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 1/3] PCI: imx6: Fix a typo in error message Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 2/3] PCI: imx6: Allow probe deferal by reset GPIO Andrey Smirnov 2017-02-06 15:17 ` [PATCH v3 3/3] PCI: imx6: Add code to support i.MX7D Andrey Smirnov 2017-02-06 15:33 ` Lucas Stach 2017-02-06 19:18 ` Andrey Smirnov
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