[PATCH 1/2] pci: ftpci100: add clock bindings

[PATCH 1/2] pci: ftpci100: add clock bindings

[Linus Walleij]

The Faraday FTPCI100 controller has two clock ports, PCLK and PCICLK.
We add bindings for these two clocks so we can assign them in the device
tree.

Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 Documentation/devicetree/bindings/pci/faraday,ftpci100.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt b/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt
index 35d4a979bb7b..89a84f8aa621 100644
--- a/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt
+++ b/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt
@@ -30,6 +30,13 @@ Mandatory properties:
   128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
   pre-fetchable.
 
+Optional properties:
+- clocks: when present, this should contain the peripheral clock (PCLK) and the
+  PCI clock (PCICLK). If these are not present, they are assumed to be
+  hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
+- clock-names: when present, this should contain "PCLK" for the peripheral
+  clock and "PCICLK" for the PCI-side clock.
+
 Mandatory subnodes:
 - For "faraday,ftpci100" a node representing the interrupt-controller inside the
   host bridge is mandatory. It has the following mandatory properties:
-- 
2.9.3

Re: [PATCH 1/2] pci: ftpci100: add clock bindings

[Rob Herring]

On Mon, May 15, 2017 at 07:23:12PM +0200, Linus Walleij wrote:
> The Faraday FTPCI100 controller has two clock ports, PCLK and PCICLK.
> We add bindings for these two clocks so we can assign them in the device
> tree.
> 
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  Documentation/devicetree/bindings/pci/faraday,ftpci100.txt | 7 +++++++
>  1 file changed, 7 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/2] pci: ftpci100: add clock bindings

[Bjorn Helgaas]

On Mon, May 15, 2017 at 07:23:12PM +0200, Linus Walleij wrote:
> The Faraday FTPCI100 controller has two clock ports, PCLK and PCICLK.
> We add bindings for these two clocks so we can assign them in the device
> tree.
> 
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Applied both (with Rob's ack on the first) to pci/host-faraday for v4.13,
thanks!

> ---
>  Documentation/devicetree/bindings/pci/faraday,ftpci100.txt | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt b/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt
> index 35d4a979bb7b..89a84f8aa621 100644
> --- a/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt
> +++ b/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt
> @@ -30,6 +30,13 @@ Mandatory properties:
>    128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
>    pre-fetchable.
>  
> +Optional properties:
> +- clocks: when present, this should contain the peripheral clock (PCLK) and the
> +  PCI clock (PCICLK). If these are not present, they are assumed to be
> +  hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
> +- clock-names: when present, this should contain "PCLK" for the peripheral
> +  clock and "PCICLK" for the PCI-side clock.
> +
>  Mandatory subnodes:
>  - For "faraday,ftpci100" a node representing the interrupt-controller inside the
>    host bridge is mandatory. It has the following mandatory properties:
> -- 
> 2.9.3
>