[Q] What about PCI mmio access alignment?

[Q] What about PCI mmio access alignment?

[Du, Changbin]

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Hi, guys,
I have a basic quesion about the alignment when access PCI bar mmio space. Is
the address accessed must be DW aligned and count must be DW aligned?

As far as I know, The address field of TLB ignore lower 2 bits and the unit of
length field also is DW. So does it mean above question is Yes? Else will CPU
handle unaligned access for mmio space?

I want to know wether below access illegal or not:
  - readb(bar0)
  - readb(bar0 + 1)
  - readl(bar0)

Thanks,
Changbin Du

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Re: [Q] What about PCI mmio access alignment?

[Andy Shevchenko]

On Thu, May 25, 2017 at 1:12 PM, Du, Changbin <changbin.du@intel.com> wrote:
> I have a basic quesion about the alignment when access PCI bar mmio space. Is
> the address accessed must be DW aligned and count must be DW aligned?

I guess the best answer is PCI architecture specification.
Book I have nearby tells me IIDnMS that yes, you have to follow alignment.

> As far as I know, The address field of TLB ignore lower 2 bits and the unit of
> length field also is DW. So does it mean above question is Yes? Else will CPU
> handle unaligned access for mmio space?

Here you perhaps meant the bus, not the CPU. PCI allows it as long as
actual device allows it.

(I recall patch series that tries to micro optimize PCI config space
access by grouping some bytes into words or even dwords, and it was
rejected).

> I want to know wether below access illegal or not:
>   - readb(bar0)
>   - readb(bar0 + 1)
>   - readl(bar0)

It depends.

-- 
With Best Regards,
Andy Shevchenko

Re: [Q] What about PCI mmio access alignment?

[Du, Changbin]

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Thank you. I have some experiment on my PC. The result is:
  o I always can get expected value if the unaligned access doesn't across a
    DWORD boundary, like readw(bar0+1). I suspect that the chipset should read
    a whole DWORD in behind. This may trigger unexpected behaviour on device.
  o If read across DWORD boundary, I get some intersting value, like
    readl(bar0+2). For some device, I get a cyclic shifted value of the first
    DWORD, while some device return all FF.

So my conclusion is that no unaligned access and at least access one DWORD size.

On Sat, May 27, 2017 at 06:32:48PM +0300, Andy Shevchenko wrote:
> On Thu, May 25, 2017 at 1:12 PM, Du, Changbin <changbin.du@intel.com> wrote:
> > I have a basic quesion about the alignment when access PCI bar mmio space. Is
> > the address accessed must be DW aligned and count must be DW aligned?
> 
> I guess the best answer is PCI architecture specification.
> Book I have nearby tells me IIDnMS that yes, you have to follow alignment.
> 
> > As far as I know, The address field of TLB ignore lower 2 bits and the unit of
> > length field also is DW. So does it mean above question is Yes? Else will CPU
> > handle unaligned access for mmio space?
> 
> Here you perhaps meant the bus, not the CPU. PCI allows it as long as
> actual device allows it.
> 
> (I recall patch series that tries to micro optimize PCI config space
> access by grouping some bytes into words or even dwords, and it was
> rejected).
> 
> > I want to know wether below access illegal or not:
> >   - readb(bar0)
> >   - readb(bar0 + 1)
> >   - readl(bar0)
> 
> It depends.
> 
> -- 
> With Best Regards,
> Andy Shevchenko

-- 
Thanks,
Changbin Du

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