PCI endpoint API question

PCI endpoint API question

[Christoph Hellwig]

Hi Kishon,

I've been looking at porting some code to the current incarnation
of your PCI endpoint API.  Once thing that I'm missing is a notification
for writes to BARs - is this and intentional omission?  It seems
like the only current option is to poll for changes.

Re: PCI endpoint API question

[Kishon Vijay Abraham I]

Hi Christoph,

On Sunday 18 June 2017 07:35 PM, Christoph Hellwig wrote:
> Hi Kishon,
> 
> I've been looking at porting some code to the current incarnation
> of your PCI endpoint API.  Once thing that I'm missing is a notification
> for writes to BARs - is this and intentional omission?  It seems
> like the only current option is to poll for changes.

You mean write to the address that's mapped to BAR in the EP side?

PCI doesn't allow hosts to interrupt the EP (AFAIK), so we have to poll for any
writes by the host to EP memory.

However recently I found "Mailbox" module in dra7xx can be used in conjunction
with PCI for PCI host to interrupt EP. I'm yet to add support for using such
SoC specific mechanisms for EP interrupts.

Thanks
Kishon

Re: PCI endpoint API question

[Christoph Hellwig]

On Mon, Jun 19, 2017 at 03:20:29PM +0530, Kishon Vijay Abraham I wrote:
> > for writes to BARs - is this and intentional omission?  It seems
> > like the only current option is to poll for changes.
> 
> You mean write to the address that's mapped to BAR in the EP side?
> 
> PCI doesn't allow hosts to interrupt the EP (AFAIK), so we have to poll for any
> writes by the host to EP memory.

At least out on the bus each MMIO access translates to PCIe Memory
Read/Write TLPs, so the EP itself for sure gets a notification.  I don't
really know enough about existing programmable endpoint IP to know
how that could be forwarded to software, though.

Re: PCI endpoint API question

[Kishon Vijay Abraham I]

Hi,

On Monday 19 June 2017 08:35 PM, Christoph Hellwig wrote:
> On Mon, Jun 19, 2017 at 03:20:29PM +0530, Kishon Vijay Abraham I wrote:
>>> for writes to BARs - is this and intentional omission?  It seems
>>> like the only current option is to poll for changes.
>>
>> You mean write to the address that's mapped to BAR in the EP side?
>>
>> PCI doesn't allow hosts to interrupt the EP (AFAIK), so we have to poll for any
>> writes by the host to EP memory.
> 
> At least out on the bus each MMIO access translates to PCIe Memory
> Read/Write TLPs, so the EP itself for sure gets a notification.  I don't
> really know enough about existing programmable endpoint IP to know
> how that could be forwarded to software, though.

yeah, at least in dra7xx I'm not aware of any way in which it is notified to
software. Off late I'm working on enabling endpoint mode in another TI platform
K2G. And there they re-use MSI register for the host to interrupt the endpoint.
See "11.14.4.16.3 Interrupt Generation in RC Mode" section in
http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf.

Thanks
Kishon