Re: DMA_ATTR_WEAK_ORDERING defintion, was Re: [PATCH] nvme: set DMA_ATTR_WEAK_ORDERING attribute on dma buffers

[Christoph Hellwig <hch@lst.de>]

On Tue, Jun 27, 2017 at 04:46:31PM -0400, chris hyser wrote:
> I put this in for SPARC. In our case the host bridge/RC itself follows very 
> strict ordering unless the relaxed order bit is set in the TLP. This works 
> great for devices that actually allow the driver to enable it. We however 
> also have to support an infiniband card that does not support enabling this 
> in the HW and thus in the TLP but is actually fine with relaxed order for 
> the data buffers (ie the streaming I/O vs the coherent control buffers). In 
> fact w/o relaxed order the performance is absolutely atrocious ... w/ 
> exceeds x86. This flag enables the driver to signal to us when we map the 
> buffer in the IOMMU to enable the relaxed order attribute for our HW.

We'll really need to start writing down our semantics.  As I said
given how our streaming dma mappings (dma_map_single/page/sg) are
defined I can't think of any way how relaxed vs strict ordering would
matter for them, so just enabling it by default seems like the right
thing in this case, instead of having to patch every PCIe driver people
might ever use on sparc to work around your bridge.