From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Date: Wed, 9 Aug 2017 11:00:08 -0700 From: "Raj, Ashok" To: Casey Leedom Cc: Bjorn Helgaas , Ding Tianhong , "bhelgaas@google.com" , Michael Werner , Ganesh GR , "asit.k.mallick@intel.com" , "patrick.j.cramer@intel.com" , "Suravee.Suthikulpanit@amd.com" , "Bob.Shaw@amd.com" , "l.stach@pengutronix.de" , "amira@mellanox.com" , "gabriele.paoloni@huawei.com" , "David.Laight@aculab.com" , "jeffrey.t.kirsher@intel.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "mark.rutland@arm.com" , "robin.murphy@arm.com" , "davem@davemloft.net" , "alexander.duyck@gmail.com" , "linux-arm-kernel@lists.infradead.org" , "netdev@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linuxarm@huawei.com" , ashok.raj@intel.com Subject: Re: [PATCH v9 1/4] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Message-ID: <20170809180007.GA9100@otc-nc-03> References: <1501917313-9812-1-git-send-email-dingtianhong@huawei.com> <1501917313-9812-2-git-send-email-dingtianhong@huawei.com> <20170808232200.GO16580@bhelgaas-glaptop.roam.corp.google.com> <20170809155841.GA8675@otc-nc-03> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: List-ID: On Wed, Aug 09, 2017 at 04:46:07PM +0000, Casey Leedom wrote: > | From: Raj, Ashok > | Sent: Wednesday, August 9, 2017 8:58 AM > | ... > | As Casey pointed out in an earlier thread, we choose the heavy hammer > | approach because there are some that can lead to data-corruption as opposed > | to perf degradation. > > Careful. As far as I'm aware, there is no Data Corruption problem > whatsoever with Intel Root Ports and processing of Transaction Layer Packets > with and without the Relaxed Ordering Attribute set. That's right.. no data-corruption on Intel parts :-).. It was with other vendor. Only performance issue with intel root-ports in the parts identified by the optimization guide. Cheers, AShok