* [PATCH v3 1/4] PCI: rockchip: Fix error handlings
2017-08-18 8:28 [PATCH v3 0/4] PCI: rockchip: Move PCIE_WAKE handling into rockchip pcie driver Jeffy Chen
@ 2017-08-18 8:28 ` Jeffy Chen
2017-08-18 8:28 ` [PATCH v3 2/4] PCI: rockchip: Add support for pcie wake irq Jeffy Chen
2017-08-18 8:28 ` [PATCH v3 3/4] dt-bindings: " Jeffy Chen
2 siblings, 0 replies; 4+ messages in thread
From: Jeffy Chen @ 2017-08-18 8:28 UTC (permalink / raw)
To: linux-kernel, bhelgaas
Cc: Jeffy Chen, Heiko Stuebner, linux-pci, shawn.lin, briannorris,
dianders, linux-rockchip, linux-arm-kernel
Fix error handlings in probe & resume.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
drivers/pci/host/pcie-rockchip.c | 103 ++++++++++++++++++++++-----------------
1 file changed, 58 insertions(+), 45 deletions(-)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 7bb9870f6d8c..e9867bcff1ff 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -546,25 +546,25 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_assert(rockchip->core_rst);
if (err) {
dev_err(dev, "assert core_rst err %d\n", err);
- return err;
+ goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
dev_err(dev, "assert mgmt_rst err %d\n", err);
- return err;
+ goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
- return err;
+ goto err_exit_phy;
}
err = reset_control_assert(rockchip->pipe_rst);
if (err) {
dev_err(dev, "assert pipe_rst err %d\n", err);
- return err;
+ goto err_exit_phy;
}
udelay(10);
@@ -572,19 +572,19 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_deassert(rockchip->pm_rst);
if (err) {
dev_err(dev, "deassert pm_rst err %d\n", err);
- return err;
+ goto err_exit_phy;
}
err = reset_control_deassert(rockchip->aclk_rst);
if (err) {
dev_err(dev, "deassert aclk_rst err %d\n", err);
- return err;
+ goto err_exit_phy;
}
err = reset_control_deassert(rockchip->pclk_rst);
if (err) {
dev_err(dev, "deassert pclk_rst err %d\n", err);
- return err;
+ goto err_exit_phy;
}
if (rockchip->link_gen == 2)
@@ -605,7 +605,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = phy_power_on(rockchip->phy);
if (err) {
dev_err(dev, "fail to power on phy, err %d\n", err);
- return err;
+ goto err_exit_phy;
}
/*
@@ -615,25 +615,25 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
if (err) {
dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
- return err;
+ goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->core_rst);
if (err) {
dev_err(dev, "deassert core_rst err %d\n", err);
- return err;
+ goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->mgmt_rst);
if (err) {
dev_err(dev, "deassert mgmt_rst err %d\n", err);
- return err;
+ goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
dev_err(dev, "deassert pipe_rst err %d\n", err);
- return err;
+ goto err_power_off_phy;
}
/* Fix the transmitted FTS count desired to exit from L0s. */
@@ -666,7 +666,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
500 * USEC_PER_MSEC);
if (err) {
dev_err(dev, "PCIe link training gen1 timeout!\n");
- return -ETIMEDOUT;
+ goto err_power_off_phy;
}
if (rockchip->link_gen == 2) {
@@ -715,6 +715,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR);
return 0;
+err_power_off_phy:
+ phy_power_off(rockchip->phy);
+err_exit_phy:
+ phy_exit(rockchip->phy);
+ return err;
}
static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
@@ -1051,7 +1056,7 @@ static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
err = regulator_enable(rockchip->vpcie3v3);
if (err) {
dev_err(dev, "fail to enable vpcie3v3 regulator\n");
- goto err_out;
+ return err;
}
}
@@ -1072,14 +1077,12 @@ static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
}
return 0;
-
err_disable_1v8:
if (!IS_ERR(rockchip->vpcie1v8))
regulator_disable(rockchip->vpcie1v8);
err_disable_3v3:
if (!IS_ERR(rockchip->vpcie3v3))
regulator_disable(rockchip->vpcie3v3);
-err_out:
return err;
}
@@ -1315,43 +1318,47 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev)
err = clk_prepare_enable(rockchip->clk_pcie_pm);
if (err)
- goto err_pcie_pm;
+ goto err_disable_0v9;
err = clk_prepare_enable(rockchip->hclk_pcie);
if (err)
- goto err_hclk_pcie;
+ goto err_disable_clk_pcie_pm;
err = clk_prepare_enable(rockchip->aclk_perf_pcie);
if (err)
- goto err_aclk_perf_pcie;
+ goto err_disable_hclk_pcie;
err = clk_prepare_enable(rockchip->aclk_pcie);
if (err)
- goto err_aclk_pcie;
+ goto err_disable_aclk_perf_pcie;
err = rockchip_pcie_init_port(rockchip);
if (err)
- goto err_pcie_resume;
+ goto err_disable_aclk_pcie;
err = rockchip_pcie_cfg_atu(rockchip);
if (err)
- goto err_pcie_resume;
+ goto err_deinit_port;
/* Need this to enter L1 again */
rockchip_pcie_update_txcredit_mui(rockchip);
rockchip_pcie_enable_interrupts(rockchip);
return 0;
-
-err_pcie_resume:
+err_deinit_port:
+ phy_power_off(rockchip->phy);
+ phy_exit(rockchip->phy);
+err_disable_aclk_pcie:
clk_disable_unprepare(rockchip->aclk_pcie);
-err_aclk_pcie:
+err_disable_aclk_perf_pcie:
clk_disable_unprepare(rockchip->aclk_perf_pcie);
-err_aclk_perf_pcie:
+err_disable_hclk_pcie:
clk_disable_unprepare(rockchip->hclk_pcie);
-err_hclk_pcie:
+err_disable_clk_pcie_pm:
clk_disable_unprepare(rockchip->clk_pcie_pm);
-err_pcie_pm:
+err_disable_0v9:
+ if (!IS_ERR(rockchip->vpcie0v9))
+ regulator_disable(rockchip->vpcie0v9);
return err;
}
@@ -1388,47 +1395,47 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
err = clk_prepare_enable(rockchip->aclk_pcie);
if (err) {
dev_err(dev, "unable to enable aclk_pcie clock\n");
- goto err_aclk_pcie;
+ return err;
}
err = clk_prepare_enable(rockchip->aclk_perf_pcie);
if (err) {
dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
- goto err_aclk_perf_pcie;
+ goto err_disable_aclk_pcie;
}
err = clk_prepare_enable(rockchip->hclk_pcie);
if (err) {
dev_err(dev, "unable to enable hclk_pcie clock\n");
- goto err_hclk_pcie;
+ goto err_disable_aclk_perf_pcie;
}
err = clk_prepare_enable(rockchip->clk_pcie_pm);
if (err) {
dev_err(dev, "unable to enable hclk_pcie clock\n");
- goto err_pcie_pm;
+ goto err_disable_hclk_pcie;
}
err = rockchip_pcie_set_vpcie(rockchip);
if (err) {
dev_err(dev, "failed to set vpcie regulator\n");
- goto err_set_vpcie;
+ goto err_disable_clk_pcie_pm;
}
err = rockchip_pcie_init_port(rockchip);
if (err)
- goto err_vpcie;
+ goto err_disable_vpcie;
rockchip_pcie_enable_interrupts(rockchip);
err = rockchip_pcie_init_irq_domain(rockchip);
if (err < 0)
- goto err_vpcie;
+ goto err_deinit_port;
err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
&res, &io_base);
if (err)
- goto err_vpcie;
+ goto err_remove_irq_domain;
err = devm_request_pci_bus_resources(dev, &res);
if (err)
@@ -1466,12 +1473,12 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
err = rockchip_pcie_cfg_atu(rockchip);
if (err)
- goto err_free_res;
+ goto err_unmap_iospace;
rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
if (!rockchip->msg_region) {
err = -ENOMEM;
- goto err_free_res;
+ goto err_unmap_iospace;
}
list_splice_init(&res, &bridge->windows);
@@ -1496,26 +1503,32 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
- return 0;
+ return 0;
+err_unmap_iospace:
+ pci_unmap_iospace(rockchip->io);
err_free_res:
pci_free_resource_list(&res);
-err_vpcie:
+err_remove_irq_domain:
+ irq_domain_remove(rockchip->irq_domain);
+err_deinit_port:
+ phy_power_off(rockchip->phy);
+ phy_exit(rockchip->phy);
+err_disable_vpcie:
if (!IS_ERR(rockchip->vpcie3v3))
regulator_disable(rockchip->vpcie3v3);
if (!IS_ERR(rockchip->vpcie1v8))
regulator_disable(rockchip->vpcie1v8);
if (!IS_ERR(rockchip->vpcie0v9))
regulator_disable(rockchip->vpcie0v9);
-err_set_vpcie:
+err_disable_clk_pcie_pm:
clk_disable_unprepare(rockchip->clk_pcie_pm);
-err_pcie_pm:
+err_disable_hclk_pcie:
clk_disable_unprepare(rockchip->hclk_pcie);
-err_hclk_pcie:
+err_disable_aclk_perf_pcie:
clk_disable_unprepare(rockchip->aclk_perf_pcie);
-err_aclk_perf_pcie:
+err_disable_aclk_pcie:
clk_disable_unprepare(rockchip->aclk_pcie);
-err_aclk_pcie:
return err;
}
--
2.11.0
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v3 2/4] PCI: rockchip: Add support for pcie wake irq
2017-08-18 8:28 [PATCH v3 0/4] PCI: rockchip: Move PCIE_WAKE handling into rockchip pcie driver Jeffy Chen
2017-08-18 8:28 ` [PATCH v3 1/4] PCI: rockchip: Fix error handlings Jeffy Chen
@ 2017-08-18 8:28 ` Jeffy Chen
2017-08-18 8:28 ` [PATCH v3 3/4] dt-bindings: " Jeffy Chen
2 siblings, 0 replies; 4+ messages in thread
From: Jeffy Chen @ 2017-08-18 8:28 UTC (permalink / raw)
To: linux-kernel, bhelgaas
Cc: Jeffy Chen, Heiko Stuebner, linux-pci, shawn.lin, briannorris,
dianders, linux-rockchip, linux-arm-kernel
Add support for PCIE_WAKE pin in rockchip pcie driver.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
---
Changes in v3:
Fix error handling
Changes in v2:
Use dev_pm_set_dedicated_wake_irq
-- Suggested by Brian Norris <briannorris@chromium.com>
drivers/pci/host/pcie-rockchip.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e9867bcff1ff..d52318458060 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -36,6 +36,7 @@
#include <linux/pci_ids.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
#include <linux/reset.h>
#include <linux/regmap.h>
@@ -858,7 +859,6 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-
/**
* rockchip_pcie_parse_dt - Parse Device Tree
* @rockchip: PCIe port information
@@ -1023,6 +1023,14 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
return err;
}
+ device_init_wakeup(dev, true);
+ irq = platform_get_irq_byname(pdev, "wake");
+ if (irq >= 0) {
+ err = dev_pm_set_dedicated_wake_irq(dev, irq);
+ if (err)
+ dev_err(dev, "failed to setup PCIe wake IRQ\n");
+ }
+
rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
if (IS_ERR(rockchip->vpcie3v3)) {
if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
@@ -1390,12 +1398,13 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
err = rockchip_pcie_parse_dt(rockchip);
if (err)
- return err;
+ /* It's safe to disable wake even not enabled */
+ goto err_disable_wake;
err = clk_prepare_enable(rockchip->aclk_pcie);
if (err) {
dev_err(dev, "unable to enable aclk_pcie clock\n");
- return err;
+ goto err_disable_wake;
}
err = clk_prepare_enable(rockchip->aclk_perf_pcie);
@@ -1529,6 +1538,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
clk_disable_unprepare(rockchip->aclk_perf_pcie);
err_disable_aclk_pcie:
clk_disable_unprepare(rockchip->aclk_pcie);
+err_disable_wake:
+ dev_pm_clear_wake_irq(dev);
+ device_init_wakeup(dev, false);
return err;
}
@@ -1557,6 +1569,9 @@ static int rockchip_pcie_remove(struct platform_device *pdev)
if (!IS_ERR(rockchip->vpcie0v9))
regulator_disable(rockchip->vpcie0v9);
+ dev_pm_clear_wake_irq(dev);
+ device_init_wakeup(dev, false);
+
return 0;
}
--
2.11.0
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v3 3/4] dt-bindings: PCI: rockchip: Add support for pcie wake irq
2017-08-18 8:28 [PATCH v3 0/4] PCI: rockchip: Move PCIE_WAKE handling into rockchip pcie driver Jeffy Chen
2017-08-18 8:28 ` [PATCH v3 1/4] PCI: rockchip: Fix error handlings Jeffy Chen
2017-08-18 8:28 ` [PATCH v3 2/4] PCI: rockchip: Add support for pcie wake irq Jeffy Chen
@ 2017-08-18 8:28 ` Jeffy Chen
2 siblings, 0 replies; 4+ messages in thread
From: Jeffy Chen @ 2017-08-18 8:28 UTC (permalink / raw)
To: linux-kernel, bhelgaas
Cc: Mark Rutland, devicetree, Jeffy Chen, Heiko Stuebner, linux-pci,
shawn.lin, briannorris, dianders, linux-rockchip, Rob Herring,
linux-arm-kernel
Add an optional interrupt for PCIE_WAKE pin.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/pci/rockchip-pcie.txt | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
index 1453a734c2f5..edd779f842fa 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -22,10 +22,13 @@ Required properties:
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
- phy-names: MUST be "pcie-phy".
- interrupts: Three interrupt entries must be specified.
-- interrupt-names: Must include the following names
- - "sys"
- - "legacy"
- - "client"
+- interrupt-names: Include the following names
+ Required:
+ - "sys"
+ - "legacy"
+ - "client"
+ Optional:
+ - "wake"
- resets: Must contain seven entries for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following names
@@ -76,10 +79,11 @@ pcie0: pcie@f8000000 {
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
bus-range = <0x0 0x1>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "legacy", "client";
+ interrupts-extended = <&gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&gpio0 8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sys", "legacy", "client", "wake";
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread