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From: Niklas Cassel <nks@flawful.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Niklas Cassel <niklas.cassel@axis.com>,
	cyrille.pitchen@free-electrons.com,
	Alan Douglas <adouglas@cadence.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Sekhar Nori <nsekhar@ti.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Niklas Cassel <niklass@axis.com>,
	John Keeping <john@metanate.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 09/12] PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar
Date: Mon, 2 Apr 2018 20:47:01 +0200	[thread overview]
Message-ID: <20180402184701.GA23587@flawful.org> (raw)
In-Reply-To: <ac3131cb-468d-5143-62a4-68d6e6b47e82@ti.com>

On Thu, Mar 29, 2018 at 03:30:23PM +0530, Kishon Vijay Abraham I wrote:
> Hi Niklas,
> 
> On Wednesday 28 March 2018 05:20 PM, Niklas Cassel wrote:
> > Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar.
> > 
> > This is needed so that epc->ops->clear_bar() can clear the BAR pair,
> > if the BAR is 64-bits wide.
> > 
> > This also makes it possible for pci_epc_clear_bar() to sanity check
> > the flags.
> > 
> > Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
> > ---
> >  drivers/pci/cadence/pcie-cadence-ep.c         |  3 ++-
> >  drivers/pci/dwc/pcie-designware-ep.c          | 13 ++++++++++---
> >  drivers/pci/endpoint/functions/pci-epf-test.c |  5 ++++-
> >  drivers/pci/endpoint/pci-epc-core.c           |  7 ++++---
> >  include/linux/pci-epc.h                       |  5 +++--
> >  5 files changed, 23 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/pci/cadence/pcie-cadence-ep.c b/drivers/pci/cadence/pcie-cadence-ep.c
> > index 2905e098678c..3d8283e450a9 100644
> > --- a/drivers/pci/cadence/pcie-cadence-ep.c
> > +++ b/drivers/pci/cadence/pcie-cadence-ep.c
> > @@ -145,10 +145,11 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
> >  }
> >  
> >  static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
> > -				   enum pci_barno bar)
> > +				   struct pci_epf_bar *epf_bar)
> >  {
> >  	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
> >  	struct cdns_pcie *pcie = &ep->pcie;
> > +	enum pci_barno bar = epf_bar->barno;
> >  	u32 reg, cfg, b, ctrl;
> >  
> >  	if (bar < BAR_4) {
> > diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
> > index 571b90f88d84..cc4d8381c1dc 100644
> > --- a/drivers/pci/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/dwc/pcie-designware-ep.c
> > @@ -19,7 +19,8 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> >  	pci_epc_linkup(epc);
> >  }
> >  
> > -void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> > +static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
> > +				   int flags)
> 
> Looks like the 'flags' are not used anywhere here?

Hello Kishon,

That is correct, this patch is simply refactoring, flags is first used
in patch 11/12, since I didn't want to refactor + add new code in the
same commit.

Kind regards,
Niklas

  reply	other threads:[~2018-04-02 18:56 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-28 11:50 [PATCH v5 00/12] PCI endpoint 64-bit BAR fixes Niklas Cassel
2018-03-28 11:50 ` [PATCH v5 01/12] PCI: endpoint: BAR width should not depend on sizeof dma_addr_t Niklas Cassel
2018-03-29  9:35   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 02/12] PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar() Niklas Cassel
2018-03-28 13:12   ` Gustavo Pimentel
2018-03-29  9:36   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 03/12] PCI: endpoint: Setting BAR_5 to 64-bits wide is invalid Niklas Cassel
2018-03-29  9:40   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 04/12] PCI: endpoint: Setting 64-bit/prefetch bit is invalid when IO is set Niklas Cassel
2018-03-29  9:42   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 05/12] PCI: endpoint: Setting a BAR size > 4 GB is invalid if 64-bit flag is not set Niklas Cassel
2018-03-29  9:42   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 06/12] PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly Niklas Cassel
2018-03-28 13:13   ` Gustavo Pimentel
2018-03-29  9:47   ` Kishon Vijay Abraham I
2018-04-02 19:37     ` Niklas Cassel
2018-04-03  5:39       ` Kishon Vijay Abraham I
2018-04-03 12:53       ` Lorenzo Pieralisi
2018-04-03 14:03         ` Niklas Cassel
2018-03-28 11:50 ` [PATCH v5 07/12] PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up Niklas Cassel
2018-03-28 13:24   ` Alan Douglas
2018-03-28 19:37     ` Bjorn Helgaas
2018-03-29 16:49       ` Alan Douglas
2018-03-28 11:50 ` [PATCH v5 08/12] PCI: endpoint: Handle 64-bit BARs properly Niklas Cassel
2018-03-29  9:50   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 09/12] PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar Niklas Cassel
2018-03-28 13:14   ` Gustavo Pimentel
2018-03-29 10:00   ` Kishon Vijay Abraham I
2018-04-02 18:47     ` Niklas Cassel [this message]
2018-03-28 11:50 ` [PATCH v5 10/12] PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing Niklas Cassel
2018-03-29 10:02   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 11/12] PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly Niklas Cassel
2018-03-28 13:14   ` Gustavo Pimentel
2018-03-29 10:03   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 12/12] misc: pci_endpoint_test: Handle " Niklas Cassel
2018-03-29 13:52 ` [PATCH v5 00/12] PCI endpoint 64-bit BAR fixes Gustavo Pimentel
2018-04-02 19:39   ` Niklas Cassel

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