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From: Niklas Cassel <nks@flawful.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Niklas Cassel <niklas.cassel@axis.com>,
	cyrille.pitchen@free-electrons.com,
	Jingoo Han <jingoohan1@gmail.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Niklas Cassel <niklass@axis.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 06/12] PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly
Date: Tue, 3 Apr 2018 16:03:10 +0200	[thread overview]
Message-ID: <20180403140310.GA28539@flawful.org> (raw)
In-Reply-To: <20180403125312.GA18128@e107981-ln.cambridge.arm.com>

On Tue, Apr 03, 2018 at 01:53:12PM +0100, Lorenzo Pieralisi wrote:
> On Mon, Apr 02, 2018 at 09:37:03PM +0200, Niklas Cassel wrote:
> > On Thu, Mar 29, 2018 at 03:17:11PM +0530, Kishon Vijay Abraham I wrote:
> > > Hi,
> > > 
> > > On Wednesday 28 March 2018 05:20 PM, Niklas Cassel wrote:
> > > > Since a 64-bit BAR consists of a BAR pair, we need to write to both
> > > > BARs in the BAR pair to setup the BAR properly.
> > > > 
> > > > Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
> > > > ---
> > > >  drivers/pci/dwc/pcie-designware-ep.c | 11 +++++++++--
> > > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
> > > > index 5a0bb53c795c..571b90f88d84 100644
> > > > --- a/drivers/pci/dwc/pcie-designware-ep.c
> > > > +++ b/drivers/pci/dwc/pcie-designware-ep.c
> > > > @@ -138,8 +138,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
> > > >  		return ret;
> > > >  
> > > >  	dw_pcie_dbi_ro_wr_en(pci);
> > > > -	dw_pcie_writel_dbi2(pci, reg, size - 1);
> > > > -	dw_pcie_writel_dbi(pci, reg, flags);
> > > > +	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > > > +		dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> > > > +		dw_pcie_writel_dbi(pci, reg, flags);
> > > > +		dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> > > > +		dw_pcie_writel_dbi(pci, reg + 4, 0);
> > > > +	} else {
> > > > +		dw_pcie_writel_dbi2(pci, reg, size - 1);
> > > > +		dw_pcie_writel_dbi(pci, reg, flags);
> > > > +	}
> > > 
> > > 
> > > I think this should work too?
> > > 	dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> > > 	dw_pcie_writel_dbi(pci, reg, flags);
> > > 
> > > 	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > > 		dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> > > 		dw_pcie_writel_dbi(pci, reg + 4, 0);
> > > 	}
> > > 
> > 
> > Hello Kishon,
> > 
> > I agree, your suggestion is more neat.
> > 
> > 
> > Kishon, please tell me if you insist that the long if-statement
> > in pci_epc_set_bar() should be split, since there are 5 different
> > conditions. Because imho, having 5 succeeding if-statements isn't
> > clearer than having 1 long if-statement.
> > 
> > If Kishon agrees with me, then the review comment in this mail
> > seems to be the only review comment.
> > And in that case, perhaps Lorenzo wouldn't mind fixing this up.
> > Or perhaps Lorenzo prefers if I reroll the whole patch series?
> 
> I updated it myself in my pci/endpoint branch, please have a look, I
> can't guarantee we can merge this for this cycle though, I will ask
> Bjorn; apologies I could not be online for a while.

Hello Lorenzo,

your pci/endpoint branch looks good.

There is no rush, merge it whenever you think is best.

Have in mind that there is EP support @ patchwork for Rockchip
and for pcie-designware-plat, so make sure to juggle all the
branches with care :)

Kind regards,
Niklas

  reply	other threads:[~2018-04-03 14:03 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-28 11:50 [PATCH v5 00/12] PCI endpoint 64-bit BAR fixes Niklas Cassel
2018-03-28 11:50 ` [PATCH v5 01/12] PCI: endpoint: BAR width should not depend on sizeof dma_addr_t Niklas Cassel
2018-03-29  9:35   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 02/12] PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar() Niklas Cassel
2018-03-28 13:12   ` Gustavo Pimentel
2018-03-29  9:36   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 03/12] PCI: endpoint: Setting BAR_5 to 64-bits wide is invalid Niklas Cassel
2018-03-29  9:40   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 04/12] PCI: endpoint: Setting 64-bit/prefetch bit is invalid when IO is set Niklas Cassel
2018-03-29  9:42   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 05/12] PCI: endpoint: Setting a BAR size > 4 GB is invalid if 64-bit flag is not set Niklas Cassel
2018-03-29  9:42   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 06/12] PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly Niklas Cassel
2018-03-28 13:13   ` Gustavo Pimentel
2018-03-29  9:47   ` Kishon Vijay Abraham I
2018-04-02 19:37     ` Niklas Cassel
2018-04-03  5:39       ` Kishon Vijay Abraham I
2018-04-03 12:53       ` Lorenzo Pieralisi
2018-04-03 14:03         ` Niklas Cassel [this message]
2018-03-28 11:50 ` [PATCH v5 07/12] PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up Niklas Cassel
2018-03-28 13:24   ` Alan Douglas
2018-03-28 19:37     ` Bjorn Helgaas
2018-03-29 16:49       ` Alan Douglas
2018-03-28 11:50 ` [PATCH v5 08/12] PCI: endpoint: Handle 64-bit BARs properly Niklas Cassel
2018-03-29  9:50   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 09/12] PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar Niklas Cassel
2018-03-28 13:14   ` Gustavo Pimentel
2018-03-29 10:00   ` Kishon Vijay Abraham I
2018-04-02 18:47     ` Niklas Cassel
2018-03-28 11:50 ` [PATCH v5 10/12] PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing Niklas Cassel
2018-03-29 10:02   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 11/12] PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly Niklas Cassel
2018-03-28 13:14   ` Gustavo Pimentel
2018-03-29 10:03   ` Kishon Vijay Abraham I
2018-03-28 11:50 ` [PATCH v5 12/12] misc: pci_endpoint_test: Handle " Niklas Cassel
2018-03-29 13:52 ` [PATCH v5 00/12] PCI endpoint 64-bit BAR fixes Gustavo Pimentel
2018-04-02 19:39   ` Niklas Cassel

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