From: Christoph Hellwig <hch@lst.de>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"Wesley W . Terpstra" <wesley@sifive.com>,
linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: add support for Xilinx PCIe root ports on RISC-V
Date: Tue, 19 Jun 2018 16:16:57 +0200 [thread overview]
Message-ID: <20180619141700.7842-1-hch@lst.de> (raw)
Hi all,
this series with patches originally from Palmer and Wesley adds support
for the pcie-xilinx host driver on RISC-V boards. The interesting part
about that is that the IP blocks is limited to 32-bit DMA internally,
which didn't seem to be an issue with the existing users, but shows
up easily with the Sifive RISC-V boards that have physical memory
wired up above 4G. To support this the per-device flag I've added last
merge window is set through a new hook in struct pci_ops.
next reply other threads:[~2018-06-19 14:17 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-19 14:16 Christoph Hellwig [this message]
2018-06-19 14:16 ` [PATCH 1/3] PCI: Add hooks for bus/bridge-specific fixups Christoph Hellwig
2018-06-19 14:31 ` Arnd Bergmann
2018-06-19 17:32 ` Christoph Hellwig
2018-06-19 18:48 ` Sinan Kaya
2018-06-19 14:16 ` [PATCH 2/3] PCI/xilinx: Work-around for hardware DMA limit (32 bits) Christoph Hellwig
2018-06-19 14:17 ` [PATCH 3/3] PCI/xilinx: Depend on OF instead of the ARCH Christoph Hellwig
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