From: Christoph Hellwig <hch@lst.de>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"Wesley W . Terpstra" <wesley@sifive.com>,
linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH 1/3] PCI: Add hooks for bus/bridge-specific fixups
Date: Tue, 19 Jun 2018 16:16:58 +0200 [thread overview]
Message-ID: <20180619141700.7842-2-hch@lst.de> (raw)
In-Reply-To: <20180619141700.7842-1-hch@lst.de>
From: "Wesley W. Terpstra" <wesley@sifive.com>
There is currently no way for a PCIe bridge to impose constraints on
devices added to it. For example, the Xilinx PCIe host bridge only
supports 32-bit physical addresses (due to a limitation on the AXI
port's address width). Thus, even devices that claim to support 64-bit
DMA addresses must be restricted to 32-bit addresses when attached to
this host controller.
This patch adds at "add_dev" hook to pci_ops that allows the PCI
infastructure to interpose when adding a device, which in the case of
the Xilinx driver will be used to restrict the address ranges used for
DMA.
Signed-off-by: Wesley W. Terpstra <wesley@sifive.com>
[hch: simplified the prototype]
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
drivers/pci/probe.c | 3 +++
include/linux/pci.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac876e32de4b..978e684cba2c 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2331,6 +2331,9 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
/* Set up MSI IRQ domain */
pci_set_msi_domain(dev);
+ if (bus->ops->add_dev)
+ bus->ops->add_dev(dev, bus);
+
/* Notifier could use PCI capabilities */
dev->match_driver = false;
ret = device_add(&dev->dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 340029b2fb38..ea9609fc44fc 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -662,6 +662,7 @@ static inline int pcibios_err_to_errno(int err)
struct pci_ops {
int (*add_bus)(struct pci_bus *bus);
void (*remove_bus)(struct pci_bus *bus);
+ void (*add_dev)(struct pci_dev *dev, struct pci_bus *bus);
void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
--
2.17.1
next prev parent reply other threads:[~2018-06-19 14:17 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-19 14:16 add support for Xilinx PCIe root ports on RISC-V Christoph Hellwig
2018-06-19 14:16 ` Christoph Hellwig [this message]
2018-06-19 14:31 ` [PATCH 1/3] PCI: Add hooks for bus/bridge-specific fixups Arnd Bergmann
2018-06-19 17:32 ` Christoph Hellwig
2018-06-19 18:48 ` Sinan Kaya
2018-06-19 14:16 ` [PATCH 2/3] PCI/xilinx: Work-around for hardware DMA limit (32 bits) Christoph Hellwig
2018-06-19 14:17 ` [PATCH 3/3] PCI/xilinx: Depend on OF instead of the ARCH Christoph Hellwig
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180619141700.7842-2-hch@lst.de \
--to=hch@lst.de \
--cc=bhelgaas@google.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=palmer@dabbelt.com \
--cc=wesley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).