From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54008C43382 for ; Tue, 25 Sep 2018 08:30:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A34EE214AB for ; Tue, 25 Sep 2018 08:30:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oqRRqMST" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A34EE214AB Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-pci-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728199AbeIYOgN (ORCPT ); Tue, 25 Sep 2018 10:36:13 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55640 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726125AbeIYOgM (ORCPT ); Tue, 25 Sep 2018 10:36:12 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8P8Tbxw009067; Tue, 25 Sep 2018 03:29:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537864177; bh=G34/AhswT8fOY3yqk7Zc580LLfv4PvRh4GF91gMUaWI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oqRRqMSTZZivLKuKztmb3RZG/7LnIb/fUodFa9/WBW7jcjnY+0hCi+VH7LRbcDS77 b+WuV1JPkMDmTOSzYvaE9geTAwKjnocwkLsPAmNHC8O10wulCWz0ACxLBBo2k4qWb3 BDRouw96PzHG0HjdlkIiFr4P5kvOHWdTCBPx1kY8= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8P8TbK9007537; Tue, 25 Sep 2018 03:29:37 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 25 Sep 2018 03:29:36 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 25 Sep 2018 03:29:36 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8P8TU3l006331; Tue, 25 Sep 2018 03:29:34 -0500 From: Vignesh R To: Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , , , , , Vignesh R Subject: [PATCH v5 1/2] dt-bindings: PCI: dra7xx: Add bindings for unaligned access in host mode Date: Tue, 25 Sep 2018 14:00:23 +0530 Message-ID: <20180925083024.6960-2-vigneshr@ti.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180925083024.6960-1-vigneshr@ti.com> References: <20180925083024.6960-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update device tree binding documentation of TI's dra7xx PCI controller for enabling unaligned mem access as applicable not just in EP mode but in host mode as well. Signed-off-by: Vignesh R Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 7f7af3044016..452fe48c4fdd 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -26,6 +26,11 @@ HOST MODE ranges, interrupt-map-mask, interrupt-map : as specified in ../designware-pcie.txt + - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument + should contain the register offset within syscon + and the 2nd argument should contain the bit field + for setting the bit to enable unaligned + access. DEVICE MODE =========== -- 2.19.0