From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Trent Piepho <tpiepho@impinj.com>
Cc: "marc.zyngier@arm.com" <marc.zyngier@arm.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
"joao.pinto@synopsys.com" <joao.pinto@synopsys.com>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"faiz_abbas@ti.com" <faiz_abbas@ti.com>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"vigneshr@ti.com" <vigneshr@ti.com>
Subject: Re: [PATCH] PCI: dwc: Fix interrupt race in when handling MSI
Date: Tue, 13 Nov 2018 10:36:46 +0000 [thread overview]
Message-ID: <20181113103646.GA11202@e107981-ln.cambridge.arm.com> (raw)
In-Reply-To: <1542071920.30311.411.camel@impinj.com>
On Tue, Nov 13, 2018 at 01:18:41AM +0000, Trent Piepho wrote:
[...]
> > Based on the information provided, its very likely that I should use the
> > PCIE_MSI_INTR0_MASK register instead of PCIE_MSI_INTR0_ENABLE on the
> > dw_pci_bottom_mask() and dw_pci_bottom_unmask() callbacks. As soon as I return
> > from Linux plumbers conference, I will test the system using the
> > PCIE_MSI_INTR0_MASK register.
>
> Using enable to mask the interrupt is broken. It will allow an MSI to
> be lost if it arrives while the MSI in not enabled. It is impossible
> to prevent that from racing against the pci device driver's final check
> that no MSI-signaled condition in the hardware is present.
That's exactly why I raised the point. I would like to understand if
this means that this revert is not enough to fix the underlying issue
or we need this revert AND correct mask/unmask operations.
Thanks,
Lorenzo
next prev parent reply other threads:[~2018-11-13 10:36 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-27 0:00 [PATCH] PCI: dwc: Fix interrupt race in when handling MSI Trent Piepho
2018-11-05 10:28 ` Vignesh R
2018-11-05 12:08 ` Gustavo Pimentel
2018-11-06 14:53 ` Lorenzo Pieralisi
2018-11-06 16:00 ` Marc Zyngier
2018-11-06 19:40 ` Trent Piepho
2018-11-07 11:07 ` Lorenzo Pieralisi
2018-11-07 12:58 ` Gustavo Pimentel
2018-11-07 18:41 ` Marc Zyngier
2018-11-07 20:17 ` Trent Piepho
2018-11-08 9:49 ` Marc Zyngier
2018-11-08 19:49 ` Trent Piepho
2018-11-09 10:13 ` Lorenzo Pieralisi
2018-11-09 17:17 ` Vignesh R
2018-11-09 11:34 ` Marc Zyngier
2018-11-09 18:53 ` Trent Piepho
2018-11-13 0:41 ` Gustavo Pimentel
2018-11-13 1:18 ` Trent Piepho
2018-11-13 10:36 ` Lorenzo Pieralisi [this message]
2018-11-13 18:55 ` Trent Piepho
2018-11-13 14:40 ` Marc Zyngier
2018-11-07 12:57 ` Gustavo Pimentel
2018-11-07 18:32 ` Trent Piepho
2018-11-08 11:46 ` Gustavo Pimentel
2018-11-08 20:51 ` Trent Piepho
2018-11-12 16:01 ` Lorenzo Pieralisi
2018-11-13 1:03 ` Gustavo Pimentel
2018-11-14 21:29 ` Trent Piepho
2018-11-12 23:45 ` Gustavo Pimentel
2018-11-07 18:46 ` Marc Zyngier
2018-11-08 11:24 ` Gustavo Pimentel
2018-11-06 18:59 ` Trent Piepho
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