From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <linux-pci@vger.kernel.org>
Cc: <linuxarm@huawei.com>, Bjorn Helgaas <bhelgaas@google.com>,
<linux-arm-kernel@lists.infradead.org>,
Will Deacon <will.deacon@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Keith Busch <keith.busch@intel.com>,
"Zhou Wang" <wangzhou1@hisilicon.com>,
Shaokun Zhang <zhangshaokun@hisilicon.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [RFC PATCH 1/2] pci/portdrv: Allow for vendor defined performance monitoring units.
Date: Fri, 14 Dec 2018 21:10:54 +0800 [thread overview]
Message-ID: <20181214131055.52253-2-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20181214131055.52253-1-Jonathan.Cameron@huawei.com>
When originally introduced (and still in the docs) it was possible to have
drivers matched by HID, now it isn't so this is a bit ugly in that it will
call any registered PMU driver.
How would people prefer this was done?
* Drop the association with the port and handle as uncore.
Whilst the driver that follows is not in config space, it is likely that
future PMU units will use DVSEC (in PCI config space) and so this option
won't really be available.
* Put a full subsystem style driver matching layer in here.
Moderately simple to do do and well understood.
Right now this code is a hack to get the conversation going!
It would be nice if there was a standard PCIe PMU specification but whilst
there isn't, everyone will end up doing it differently...
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/pci/pcie/portdrv.h | 4 +++-
drivers/pci/pcie/portdrv_core.c | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h
index e495f04394d0..64315713a93d 100644
--- a/drivers/pci/pcie/portdrv.h
+++ b/drivers/pci/pcie/portdrv.h
@@ -20,8 +20,10 @@
#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
#define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
+#define PCIE_PORT_SERVICE_PMU_SHIFT 4 /* Vendor defined Perf Units */
+#define PCIE_PORT_SERVICE_PMU (1 << PCIE_PORT_SERVICE_PMU_SHIFT)
-#define PCIE_PORT_DEVICE_MAXSERVICES 4
+#define PCIE_PORT_DEVICE_MAXSERVICES 5
#ifdef CONFIG_PCIEAER
int pcie_aer_init(void);
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index f458ac9cb70c..c032896a9ab1 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -250,6 +250,8 @@ static int get_port_device_capability(struct pci_dev *dev)
pci_aer_available() && services & PCIE_PORT_SERVICE_AER)
services |= PCIE_PORT_SERVICE_DPC;
+ services |= PCIE_PORT_SERVICE_PMU;
+
return services;
}
--
2.19.1
next prev parent reply other threads:[~2018-12-14 13:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-14 13:10 [RFC PATCH 0/2] Support HiSilicon PCIe Transport Layer PMU Jonathan Cameron
2018-12-14 13:10 ` Jonathan Cameron [this message]
2018-12-14 13:10 ` [RFC PATCH 2/2] PCI/portdrv Hisilicon PCIe transport layer Port PMU driver Jonathan Cameron
2018-12-14 23:55 ` Bjorn Helgaas
2018-12-17 11:09 ` Jonathan Cameron
2018-12-17 18:19 ` Bjorn Helgaas
2018-12-17 18:34 ` Logan Gunthorpe
2018-12-18 10:21 ` Jonathan Cameron
2019-01-03 15:44 ` Will Deacon
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