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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id n126sm970310oif.19.2019.02.22.11.57.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 11:57:58 -0800 (PST) Date: Fri, 22 Feb 2019 13:57:58 -0600 From: Rob Herring To: Bjorn Andersson Cc: Mark Rutland , Kishon Vijay Abraham I , Andy Gross , David Brown , Bjorn Helgaas , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Lorenzo Pieralisi , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v2 2/7] dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY Message-ID: <20190222195758.GA26984@bogus> References: <20190219060407.15263-1-bjorn.andersson@linaro.org> <20190219060407.15263-3-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190219060407.15263-3-bjorn.andersson@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Mon, Feb 18, 2019 at 10:04:02PM -0800, Bjorn Andersson wrote: > The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of > Qualcomm platforms, add a binding to describe this. > > Signed-off-by: Bjorn Andersson > --- > .../bindings/phy/qcom-pcie2-phy.txt | 40 +++++++++++++++++++ > 1 file changed, 40 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt > > diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt > new file mode 100644 > index 000000000000..7da02f9d78c7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt > @@ -0,0 +1,40 @@ > +Qualcomm PCIe2 PHY controller > +============================= > + > +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm > +platforms. > + > +Required properties: > + - compatible: compatible list, should be: > + "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" > + > + - reg: offset and length of the PHY register set. > + - #phy-cells: must be 0. > + > + - clocks: a clock-specifier pair for the "pipe" clock > + > + - vdda-vp-supply: phandle to low voltage regulator > + - vdda-vph-supply: phandle to high voltage regulator > + > + - resets: reset-specifier pairs for the "phy" and "pipe" resets > + - reset-names: list of resets, should contain: > + "phy" and "pipe" > + > + - clock-output-names: name of the outgoing clock signal from the PHY PLL Not valid to have this without '#clock-cells'. Though I'm confused how this and the input clock name seem to match. > + > +Example: > + phy@7786000 { > + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; > + reg = <0x07786000 0xb8>; > + > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; > + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, > + <&gcc GCC_PCIE_0_PIPE_ARES>; > + reset-names = "phy", "pipe"; > + > + vdda-vp-supply = <&vreg_l3_1p05>; > + vdda-vph-supply = <&vreg_l5_1p8>; > + > + clock-output-names = "pcie_0_pipe_clk"; > + #phy-cells = <0>; > + }; > -- > 2.18.0 >