From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA0AFC4360F for ; Fri, 5 Apr 2019 12:46:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 90973218AC for ; Fri, 5 Apr 2019 12:46:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729822AbfDEMqv (ORCPT ); Fri, 5 Apr 2019 08:46:51 -0400 Received: from foss.arm.com ([217.140.101.70]:48002 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726730AbfDEMqv (ORCPT ); Fri, 5 Apr 2019 08:46:51 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11ED31688; Fri, 5 Apr 2019 05:46:51 -0700 (PDT) Received: from red-moon (unknown [10.1.197.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C49A73F557; Fri, 5 Apr 2019 05:46:48 -0700 (PDT) Date: Fri, 5 Apr 2019 13:46:44 +0100 From: Lorenzo Pieralisi To: Vidya Sagar Cc: bhelgaas@google.com, vidya sagar , treding@nvidia.com, swarren@nvidia.com, mperttunen@nvidia.com, jonathanh@nvidia.com, dev@lynxeye.de, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, kthota@nvidia.com, NManikanta Subject: Re: [PATCH V2] PCI: tegra: Use the DMA-API to get the MSI address Message-ID: <20190405124644.GA28755@red-moon> References: <1553004121-24606-1-git-send-email-vidyas@nvidia.com> <9b6c7289-cc43-4fad-dcb0-97b4413ffd42@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9b6c7289-cc43-4fad-dcb0-97b4413ffd42@nvidia.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, Apr 05, 2019 at 03:00:36AM +0530, Vidya Sagar wrote: > On 4/1/2019 11:13 AM, Vidya Sagar wrote: > > Hi Bjorn / Lorenzo, > Apologies for reminding you again. Could you please review this patch? It is in the patchwork queue - I will get to it, thank you for your patience. Lorenzo > Thanks, > Vidya Sagar > > >Hi Bjorn / Lorenzo, > >Can you please review this patch? > > > >Thanks, > >Vidya Sagar > > > >On 3/27/2019 4:29 PM, vidya sagar wrote: > >>Hi Bjorn/Lorenzo, > >>Can you please review this patch? > >>Thierry has reviewed it and I already took care of his comments. > >> > >>Thanks, > >>Vidya Sagar > >> > >>On Tue, Mar 19, 2019 at 7:33 PM Vidya Sagar > wrote: > >> > >>    Since the upstream MSI memory writes are generated by downstream devices, > >>    it is logically correct to have MSI target memory coming from the DMA pool > >>    reserved for PCIe than from the general memory pool reserved for CPU > >>    access. This avoids PCIe DMA addresses coinciding with MSI target address > >>    thereby raising unwanted MSI interrupts. This patch also enforces to limit > >>    the MSI target address to 32-bits to make it work for PCIe endponits that > >>    support only 32-bit MSI target address and those endpoints that support > >>    64-bit MSI target address anyway work with 32-bit MSI target address. > >> > >>    Signed-off-by: Vidya Sagar > > >>    Reviewed-by: Thierry Reding > > >>    Acked-by: Thierry Reding > > >>    --- > >>    v2: > >>    * changed 'phys' type to 'dma_addr_t' from 'u64' > >>    * added a comment on why DMA mask is set to 32-bit > >>    * replaced 'dma' with 'DMA' > >> > >>      drivers/pci/controller/pci-tegra.c | 35 ++++++++++++++++++++++++++--------- > >>      1 file changed, 26 insertions(+), 9 deletions(-) > >> > >>    diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c > >>    index f4f53d092e00..f8173a5e352d 100644 > >>    --- a/drivers/pci/controller/pci-tegra.c > >>    +++ b/drivers/pci/controller/pci-tegra.c > >>    @@ -231,9 +231,9 @@ struct tegra_msi { > >>             struct msi_controller chip; > >>             DECLARE_BITMAP(used, INT_PCI_MSI_NR); > >>             struct irq_domain *domain; > >>    -       unsigned long pages; > >>             struct mutex lock; > >>    -       u64 phys; > >>    +       void *virt; > >>    +       dma_addr_t phys; > >>             int irq; > >>      }; > >> > >>    @@ -1536,7 +1536,7 @@ static int tegra_pcie_msi_setup(struct tegra_pcie *pcie) > >>             err = platform_get_irq_byname(pdev, "msi"); > >>             if (err < 0) { > >>                     dev_err(dev, "failed to get IRQ: %d\n", err); > >>    -               goto err; > >>    +               goto free_irq_domain; > >>             } > >> > >>             msi->irq = err; > >>    @@ -1545,17 +1545,34 @@ static int tegra_pcie_msi_setup(struct tegra_pcie *pcie) > >>    tegra_msi_irq_chip.name , pcie); > >>             if (err < 0) { > >>                     dev_err(dev, "failed to request IRQ: %d\n", err); > >>    -               goto err; > >>    +               goto free_irq_domain; > >>    +       } > >>    + > >>    +       /* Though the PCIe controller can address >32-bit address space, to > >>    +        * facilitate endpoints that support only 32-bit MSI target address, > >>    +        * the mask is set to 32-bit to make sure that MSI target address is > >>    +        * always a 32-bit address > >>    +        */ > >>    +       err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); > >>    +       if (err < 0) { > >>    +               dev_err(dev, "failed to set DMA coherent mask: %d\n", err); > >>    +               goto free_irq; > >>    +       } > >>    + > >>    +       msi->virt = dma_alloc_coherent(dev, PAGE_SIZE, &msi->phys, GFP_KERNEL); > >>    +       if (!msi->virt) { > >>    +               dev_err(dev, "failed to allocate DMA memory for MSI\n"); > >>    +               err = -ENOMEM; > >>    +               goto free_irq; > >>             } > >> > >>    -       /* setup AFI/FPCI range */ > >>    -       msi->pages = __get_free_pages(GFP_KERNEL, 0); > >>    -       msi->phys = virt_to_phys((void *)msi->pages); > >>             host->msi = &msi->chip; > >> > >>             return 0; > >> > >>    -err: > >>    +free_irq: > >>    +       free_irq(msi->irq, pcie); > >>    +free_irq_domain: > >>             irq_domain_remove(msi->domain); > >>             return err; > >>      } > >>    @@ -1592,7 +1609,7 @@ static void tegra_pcie_msi_teardown(struct tegra_pcie *pcie) > >>             struct tegra_msi *msi = &pcie->msi; > >>             unsigned int i, irq; > >> > >>    -       free_pages(msi->pages, 0); > >>    +       dma_free_coherent(pcie->dev, PAGE_SIZE, msi->virt, msi->phys); > >> > >>             if (msi->irq > 0) > >>                     free_irq(msi->irq, pcie); > >>    --     2.7.4 > >> > > >