From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 502F5C10F14 for ; Thu, 11 Apr 2019 17:04:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 216212082E for ; Thu, 11 Apr 2019 17:04:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="E05moC7A" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726882AbfDKREp (ORCPT ); Thu, 11 Apr 2019 13:04:45 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15197 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726862AbfDKREp (ORCPT ); Thu, 11 Apr 2019 13:04:45 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 11 Apr 2019 10:04:28 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 11 Apr 2019 10:04:44 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 11 Apr 2019 10:04:44 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:04:44 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 11 Apr 2019 17:04:41 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH 05/30] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Date: Thu, 11 Apr 2019 22:33:30 +0530 Message-ID: <20190411170355.6882-6-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411170355.6882-1-mmaddireddy@nvidia.com> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555002268; bh=Qa9ljs/XutVL06IykjznecwnTGBW+nLtgXDWlJAGvtE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=E05moC7AM/+KFcj9kBBhZz8DqC78NxX698S5cdj4LXCGyzGW7GXNkwubOhViIQdeU 9ubNPN7J2lARSJlY3gHSYsiHe2ydYwuF+Li9TQ1eKthzVE4oX4VNVRpjL4FY+cHZBg KfQToQVWIwox9yQLEnH6L+JX8zJ8c9ATaGdS9E+LxiYU1PKs+gSY0bnYLTGekBzKRq iNCDRLuc2iagEKEu8KW6bn51MM6CWZT6D0hOTfh8p+DaG2pcSOzDW8HD9ypBecvjVD o+1leNAj14iRuFMJlkSC5EkTNrrKRiaDwkmRWtUBfesnY6tONVAcANvYHdbLaO6bhu Zth1I55/vj0xQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Default root port setting hides AER capability. This patch enables the advertisement of AER capability by root port. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/pci-tegra.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 6ccda82735f8..9ff1a0e2797f 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -180,6 +180,9 @@ #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_CTL1 0x00000f48 +#define RP_VEND_CTL1_ERPT (1 << 13) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -478,6 +481,16 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) afi_writel(port->pcie, value, ctrl); } +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) +{ + u32 value; + + /* Enable AER capability */ + value = readl(port->base + RP_VEND_CTL1); + value |= RP_VEND_CTL1_ERPT; + writel(value, port->base + RP_VEND_CTL1); +} + static void tegra_pcie_port_enable(struct tegra_pcie_port *port) { unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); @@ -502,6 +515,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port) value |= RP_VEND_CTL2_PCA_ENABLE; writel(value, port->base + RP_VEND_CTL2); } + + tegra_pcie_enable_rp_features(port); } static void tegra_pcie_port_disable(struct tegra_pcie_port *port) -- 2.17.1