From: Bjorn Helgaas <helgaas@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Arnd Bergmann <arnd@arndb.de>,
Murali Karicheri <m-karicheri2@ti.com>,
Jingoo Han <jingoohan1@gmail.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-arm-kernel@axis.com
Subject: Re: [PATCH v2 23/26] PCI: designware-ep: Configure RESBAR to advertise the smallest size
Date: Sat, 13 Apr 2019 11:00:53 -0500 [thread overview]
Message-ID: <20190413160053.GI126710@google.com> (raw)
In-Reply-To: <20190325083501.8088-24-kishon@ti.com>
On Mon, Mar 25, 2019 at 02:04:58PM +0530, Kishon Vijay Abraham I wrote:
> Configure RESBAR capability to advertise the smallest size (1MB) for
> couple of reasons. A) Host side resource allocation of BAR fails for
> larger sizes. B) Endpoint function driver does not allocate memory
> for all supported sizes in RESBAR capability.
> If and when there is a usecase required to add more flexibility using
> RESBAR, this can be revisited.
The #define used in the code below is "REBAR"; maybe spell it out
once and then use REBAR instead of RESBAR?
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 74477ad7467f..0c208b9bda43 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -504,10 +504,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> pci_epc_mem_exit(epc);
> }
>
> +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
> +{
> + u32 header;
> + int pos = PCI_CFG_SPACE_SIZE;
> +
> + while (pos) {
> + header = dw_pcie_readl_dbi(pci, pos);
> + if (PCI_EXT_CAP_ID(header) == cap)
> + return pos;
> +
> + pos = PCI_EXT_CAP_NEXT(header);
> + if (!pos)
> + break;
> + }
> +
> + return 0;
> +}
> +
> int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> + int i;
> int ret;
> + u32 reg;
> void *addr;
> + unsigned int nbars;
> + unsigned int offset;
> struct pci_epc *epc;
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct device *dev = pci->dev;
> @@ -591,6 +613,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>
> ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
>
> + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
> + if (offset) {
> + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
> + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
> + PCI_REBAR_CTRL_NBAR_SHIFT;
> +
> + dw_pcie_dbi_ro_wr_en(pci);
> + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
> + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
> + dw_pcie_dbi_ro_wr_dis(pci);
> + }
> +
> dw_pcie_setup(pci);
>
> return 0;
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-04-13 16:01 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-25 8:34 [PATCH v2 00/26] Add support for PCIe RC and EP mode in TI's AM654 SoC Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 01/26] PCI: keystone: Add start_link/stop_link dw_pcie_ops Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 02/26] PCI: keystone: Cleanup error_irq configuration Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 03/26] dt-bindings: PCI: keystone: Add "reg-names" binding information Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 04/26] PCI: keystone: Perform host initialization in a single function Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 05/26] PCI: keystone: Use platform_get_resource_byname to get memory resources Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 06/26] PCI: keystone: Move initializations to appropriate places Kishon Vijay Abraham I
2019-04-13 14:30 ` Bjorn Helgaas
2019-04-15 5:34 ` Kishon Vijay Abraham I
2019-04-15 12:25 ` Lorenzo Pieralisi
2019-03-25 8:34 ` [PATCH v2 07/26] dt-bindings: PCI: Add dt-binding to configure PCIe mode Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 08/26] PCI: keystone: Explicitly set the " Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 09/26] dt-bindings: PCI: Document "atu" reg-names Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 10/26] PCI: dwc: Enable iATU unroll for endpoint too Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80 Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 12/26] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 13/26] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 14/26] PCI: keystone: Add support for PCIe RC in AM654x Platforms Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 15/26] PCI: keystone: Invoke phy_reset API before enabling PHY Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 16/26] PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 17/26] PCI: keystone: Add support to set the max link speed from DT Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 18/26] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 19/26] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 20/26] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 21/26] PCI: dwc: Add callbacks for accessing dbi2 address space Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 22/26] PCI: keystone: Add support for PCIe EP in AM654x Platforms Kishon Vijay Abraham I
2019-03-25 8:34 ` [PATCH v2 23/26] PCI: designware-ep: Configure RESBAR to advertise the smallest size Kishon Vijay Abraham I
2019-04-13 16:00 ` Bjorn Helgaas [this message]
2019-04-16 13:36 ` Lorenzo Pieralisi
2019-03-25 8:34 ` [PATCH v2 24/26] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Kishon Vijay Abraham I
2019-03-25 8:35 ` [PATCH v2 25/26] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Kishon Vijay Abraham I
2019-03-25 8:35 ` [PATCH v2 26/26] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Kishon Vijay Abraham I
2019-03-25 9:36 ` [PATCH v2 00/26] Add support for PCIe RC and EP mode in TI's AM654 SoC Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190413160053.GI126710@google.com \
--to=helgaas@kernel.org \
--cc=arnd@arndb.de \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=kishon@ti.com \
--cc=linux-arm-kernel@axis.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-omap@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=m-karicheri2@ti.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).