From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 924AAC282DD for ; Tue, 23 Apr 2019 09:31:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5F487214AE for ; Tue, 23 Apr 2019 09:31:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="UNi2/fyQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727094AbfDWJbJ (ORCPT ); Tue, 23 Apr 2019 05:31:09 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8047 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726045AbfDWJbJ (ORCPT ); Tue, 23 Apr 2019 05:31:09 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Apr 2019 02:31:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 23 Apr 2019 02:31:08 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 23 Apr 2019 02:31:08 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 09:31:08 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Tue, 23 Apr 2019 09:31:05 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 27/28] PCI: tegra: Add support for GPIO based PCIe reset Date: Tue, 23 Apr 2019 14:58:24 +0530 Message-ID: <20190423092825.759-28-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423092825.759-1-mmaddireddy@nvidia.com> References: <20190423092825.759-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556011875; bh=jNyMkSAL4y6EDOG6FDzxQQZJhkz3AOGDr9sLjrFSs2o=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=UNi2/fyQm8ixhvp334s4TzUG71m939lE0f0VfE6GcD2AX7uhLQ8RGADdxdoupOS6I C8WMpS14wDroDJpE5uheomxAU3KEGqhAAHptxzJVHVNmoi0ijCykWG4brwvlPlkKS7 nuCPWBIEAV4j7Ny2NdUZxPCBwxTzVNZ0fJNeDaatBkpegNrNRb9EgqYYThzYzyU9AZ ZJxpcieSJvC7S7K+qrEoCQNeCmgg8Q2Fh+xZYQMWA7Xfy8CPHnrBosQAQnh4Pqt8XF cE6DSTm3armfIRqvAr2bHz8kRASIdeu+yrB2zUKuenNfqNJ+i1CJJJRx2lPH7bsAxU p0YFUSgF5DO2A== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for GPIO based PERST# instead of SFIO mode controlled by AFI. GPIO number comes from per port PCIe device tree node. Signed-off-by: Manikanta Maddireddy --- V2: Using standard "reset-gpio" property drivers/pci/controller/pci-tegra.c | 36 +++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 72d344858e25..09b3b3e847c5 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -400,6 +402,8 @@ struct tegra_pcie_port { unsigned int lanes; struct phy **phys; + + int reset_gpio; }; struct tegra_pcie_bus { @@ -583,15 +587,23 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) unsigned long value; /* pulse reset signal */ - value = afi_readl(port->pcie, ctrl); - value &= ~AFI_PEX_CTRL_RST; - afi_writel(port->pcie, value, ctrl); + if (gpio_is_valid(port->reset_gpio)) { + gpiod_set_value(gpio_to_desc(port->reset_gpio), 0); + } else { + value = afi_readl(port->pcie, ctrl); + value &= ~AFI_PEX_CTRL_RST; + afi_writel(port->pcie, value, ctrl); + } usleep_range(1000, 2000); - value = afi_readl(port->pcie, ctrl); - value |= AFI_PEX_CTRL_RST; - afi_writel(port->pcie, value, ctrl); + if (gpio_is_valid(port->reset_gpio)) { + gpiod_set_value(gpio_to_desc(port->reset_gpio), 1); + } else { + value = afi_readl(port->pcie, ctrl); + value |= AFI_PEX_CTRL_RST; + afi_writel(port->pcie, value, ctrl); + } } static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) @@ -2299,6 +2311,18 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) if (IS_ERR(rp->base)) return PTR_ERR(rp->base); + rp->reset_gpio = of_get_named_gpio(port, "reset-gpio", 0); + if (gpio_is_valid(rp->reset_gpio)) { + err = devm_gpio_request_one(dev, rp->reset_gpio, + GPIOF_OUT_INIT_LOW, + "pex_reset"); + if (err < 0) { + dev_err(dev, "failed to request reset-gpio: %d\n", + err); + return err; + } + } + list_add_tail(&rp->list, &pcie->ports); } -- 2.17.1