From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3248EC282E1 for ; Tue, 23 Apr 2019 09:29:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F19A7218C3 for ; Tue, 23 Apr 2019 09:29:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="jDNQ12/F" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727174AbfDWJ3K (ORCPT ); Tue, 23 Apr 2019 05:29:10 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11430 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727168AbfDWJ3J (ORCPT ); Tue, 23 Apr 2019 05:29:09 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Apr 2019 02:28:44 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 23 Apr 2019 02:29:08 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 23 Apr 2019 02:29:08 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 09:29:08 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 09:29:05 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Tue, 23 Apr 2019 09:29:01 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 07/28] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Date: Tue, 23 Apr 2019 14:58:04 +0530 Message-ID: <20190423092825.759-8-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423092825.759-1-mmaddireddy@nvidia.com> References: <20190423092825.759-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556011724; bh=6B9UY9O6qPbny94lEhs7694+v0Ip8m3Rg/+yemh9Mj4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jDNQ12/Fr+BQ2aurSWyZWs4/b6L9SNrvfAUQ9Uw2DxFsOM/I+8Zc4cFQO3pKVB8cA e+YMLQyPG+5dbEl5qu0Iy9P3aLokyZ304ozaydljNvDGVAWOYRK7RUJjgt2ted1fID r9BfltYwoqAPOfr+Dp3MQB3rHiUC1IShDbhfW73vU040PTxsp4vweYsReVk30Yk08o jNr0xFR9kqKluwqlVxB8FT7EYDunGUM3JYiRat9UwjiLKwuWVWo2IIPaLbmunh2fvv aoH2/dFw0UJ3CyrL9bTozJeG3XBpoVfMeMw44h0JV1JsnPhqbQ9mpud7MJwiE++BaH BKvlpnIgnLRMw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Default root port setting hides AER capability. This patch enables the advertisement of AER capability by root port. Signed-off-by: Manikanta Maddireddy --- V2: No change drivers/pci/controller/pci-tegra.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 0ae8ebe92bb9..11202fc2c607 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -180,6 +180,9 @@ #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_CTL1 0x00000f48 +#define RP_VEND_CTL1_ERPT (1 << 13) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -479,6 +482,16 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) afi_writel(port->pcie, value, ctrl); } +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) +{ + u32 value; + + /* Enable AER capability */ + value = readl(port->base + RP_VEND_CTL1); + value |= RP_VEND_CTL1_ERPT; + writel(value, port->base + RP_VEND_CTL1); +} + static void tegra_pcie_port_enable(struct tegra_pcie_port *port) { unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); @@ -503,6 +516,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port) value |= RP_VEND_CTL2_PCA_ENABLE; writel(value, port->base + RP_VEND_CTL2); } + + tegra_pcie_enable_rp_features(port); } static void tegra_pcie_port_disable(struct tegra_pcie_port *port) -- 2.17.1