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[46.91.239.54]) by smtp.gmail.com with ESMTPSA id f2sm8376165wmh.3.2019.05.09.07.38.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 May 2019 07:38:00 -0700 (PDT) Date: Thu, 9 May 2019 16:37:59 +0200 From: Thierry Reding To: Manikanta Maddireddy Cc: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, lorenzo.pieralisi@arm.com, vidyas@nvidia.com, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH V2 26/28] dt-bindings: pci: tegra: Document reset-gpio optional prop Message-ID: <20190509143759.GV8907@ulmo> References: <20190423092825.759-1-mmaddireddy@nvidia.com> <20190423092825.759-27-mmaddireddy@nvidia.com> <20190509143729.GU8907@ulmo> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="SZSwH5G1FJ2Fz+jP" Content-Disposition: inline In-Reply-To: <20190509143729.GU8907@ulmo> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org --SZSwH5G1FJ2Fz+jP Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, May 09, 2019 at 04:37:29PM +0200, Thierry Reding wrote: > On Tue, Apr 23, 2019 at 02:58:23PM +0530, Manikanta Maddireddy wrote: > > Document "reset-gpio" optional property which supports GPIO based PERST# > > signal. > >=20 > > Signed-off-by: Manikanta Maddireddy > > --- > > V2: Using standard "reset-gpio" property > >=20 > > .../devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 5 +++++ > > 1 file changed, 5 insertions(+) > >=20 > > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.= txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt > > index 7939bca47861..4e75e017f660 100644 > > --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt > > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt > > @@ -162,6 +162,10 @@ Required properties: > > - Root port 0 uses 4 lanes, root port 1 is unused. > > - Both root ports use 2 lanes. > > =20 > > +Optional properties: > > +- reset-gpio: If GPIO is used as PERST# signal instead of available > > + SFIO, add this property with phandle to GPIO controller and GPIO num= ber. > > + > > Required properties for Tegra124 and later: > > - phys: Must contain an phandle to a PHY for each entry in phy-names. > > - phy-names: Must include an entry for each active lane. Note that the= number > > @@ -626,6 +630,7 @@ SoC DTSI: > > ranges; > > =20 > > nvidia,num-lanes =3D <2>; > > + reset-gpio =3D <&gpio TEGRA_GPIO(A, 3) 0>; >=20 > Nit: it's customary to put vendor-specific properties below generic > ones. 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