From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A300AC43613 for ; Fri, 21 Jun 2019 09:21:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7830E2089E for ; Fri, 21 Jun 2019 09:21:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="jBK/W4RP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726460AbfFUJV6 (ORCPT ); Fri, 21 Jun 2019 05:21:58 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4549 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726210AbfFUJV5 (ORCPT ); Fri, 21 Jun 2019 05:21:57 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 21 Jun 2019 02:21:56 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 21 Jun 2019 02:21:56 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 21 Jun 2019 02:21:56 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 21 Jun 2019 09:21:56 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 21 Jun 2019 09:21:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 21 Jun 2019 09:21:55 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 21 Jun 2019 02:21:55 -0700 From: Vidya Sagar To: , , , , , , CC: , , , , , Subject: [PATCH V5 3/3] PCI: dwc: Export APIs to support .remove() implementation Date: Fri, 21 Jun 2019 14:51:27 +0530 Message-ID: <20190621092127.17930-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190621092127.17930-1-vidyas@nvidia.com> References: <20190621092127.17930-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561108916; bh=FYvdzaOFVr+ym70x/EMdYSOq8J8rrVBpAoEJx3pKPlI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jBK/W4RPh2mDanVQ6hDD7KJZdwQQ8tVllvwMPdHu1c1pFn/1O9fnmbnHuCDBbk8EH MCINnwoLn0ei+ETFs5yg8CDz4yxFe1oYkr0POABti82VIqEhQHTKu5Xh/NSv4Rgqo5 E63TvGyK4b+kOXUxvXyQEeQe2ZgqMN6oZxc2OYyef4hstWhgG4kqxRYUeXrAwQyN2/ gOSsZfUiI7R0kKL37sBe/qeM070OOwq3yqnvaXCMH4i/4da07/2irbNd4As2ym6yGT Zukx3osLIUGwA99eTI2cAtsO2nJeLnXNcupEwsRJwSFH/0svtnqpb1IH8tBDZT+vcF C8qGvLb+sdI0Q== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Export all configuration space access APIs and also other APIs to support host controller drivers of DesignWare core based implementations while adding support for .remove() hook to build their respective drivers as modules Signed-off-by: Vidya Sagar Acked-by: Gustavo Pimentel --- Changes from v4: * Removed __ (underscore) from dw_pcie_{write/read}_dbi API names Changes from v3: * Exported only __dw_pcie_{read/write}_dbi() APIs instead of dw_pcie_read{l/w/b}_dbi & dw_pcie_write{l/w/b}_dbi APIs. Changes from v2: * Rebased on top of linux-next top of the tree branch Changes from v1: * s/Designware/DesignWare drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ drivers/pci/controller/dwc/pcie-designware.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d069e4290180..f93252d0da5b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -311,6 +311,7 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, upper_32_bits(msi_target)); } +EXPORT_SYMBOL_GPL(dw_pcie_msi_init); int dw_pcie_host_init(struct pcie_port *pp) { @@ -495,6 +496,7 @@ int dw_pcie_host_init(struct pcie_port *pp) dw_pcie_free_msi(pp); return ret; } +EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct pcie_port *pp) { @@ -503,6 +505,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp) if (pci_msi_enabled() && !pp->ops->msi_host_init) dw_pcie_free_msi(pp); } +EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val, @@ -695,3 +698,4 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); } +EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 5d22028d854e..a6504295ac58 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -34,6 +34,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val) return PCIBIOS_SUCCESSFUL; } +EXPORT_SYMBOL_GPL(dw_pcie_read); int dw_pcie_write(void __iomem *addr, int size, u32 val) { @@ -51,6 +52,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } +EXPORT_SYMBOL_GPL(dw_pcie_write); u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) @@ -67,6 +69,7 @@ u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, return val; } +EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val) @@ -82,6 +85,7 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, if (ret) dev_err(pci->dev, "Write DBI address failed\n"); } +EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); u32 dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) -- 2.17.1