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[217.229.24.144]) by smtp.gmail.com with ESMTPSA id i5sm7610442wrn.48.2019.08.12.03.34.10 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 12 Aug 2019 03:34:11 -0700 (PDT) Date: Mon, 12 Aug 2019 12:34:10 +0200 From: Thierry Reding To: Vidya Sagar Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, digetx@gmail.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support Message-ID: <20190812103410.GO8903@ulmo> References: <20190809044609.20401-1-vidyas@nvidia.com> <20190812102519.GN8903@ulmo> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="mvuFargmsA+C2jC8" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org --mvuFargmsA+C2jC8 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 12, 2019 at 03:59:39PM +0530, Vidya Sagar wrote: > On 8/12/2019 3:55 PM, Thierry Reding wrote: > > On Fri, Aug 09, 2019 at 10:15:56AM +0530, Vidya Sagar wrote: > > > Tegra194 has six PCIe controllers based on Synopsys DesignWare core. > > > There are two Universal PHY (UPHY) blocks with each supporting 12(HSI= O: > > > Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively. > > > Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 u= ses > > > UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each P= CIe > > > controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe > > > core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is u= sed > > > to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bric= ks) > > > to PCIe controller > > > This patch series > > > - Adds support for P2U PHY driver > > > - Adds support for PCIe host controller > > > - Adds device tree nodes each PCIe controllers > > > - Enables nodes applicable to p2972-0000 platform > > > - Adds helper APIs in Designware core driver to get capability regs o= ffset > > > - Adds defines for new feature registers of PCIe spec revision 4 > > > - Makes changes in DesignWare core driver to get Tegra194 PCIe working > > >=20 > > > Testing done on P2972-0000 platform > > > - Able to get PCIe link up with on-board Marvel eSATA controller > > > - Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot > > > - Able to do data transfers with both SATA drives and NVMe cards > > > - Able to perform suspend-resume sequence > >=20 > > Do you happen to have a patch for P2972-0000 PCI support? I don't see it > > in this series. > It is already merged. > V10 link @ http://patchwork.ozlabs.org/patch/1114445/ D'oh! Indeed. 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