From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85E8CC4360C for ; Fri, 4 Oct 2019 10:32:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5A2AD207FF for ; Fri, 4 Oct 2019 10:32:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729529AbfJDKcb (ORCPT ); Fri, 4 Oct 2019 06:32:31 -0400 Received: from foss.arm.com ([217.140.110.172]:41162 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725907AbfJDKcb (ORCPT ); Fri, 4 Oct 2019 06:32:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5310515A1; Fri, 4 Oct 2019 03:32:30 -0700 (PDT) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A88D93F706; Fri, 4 Oct 2019 03:32:29 -0700 (PDT) Date: Fri, 4 Oct 2019 11:32:28 +0100 From: Andrew Murray To: Fabrizio Castro Cc: Geert Uytterhoeven , Rob Herring , Mark Rutland , Mark Brown , Wim Van Sebroeck , Guenter Roeck , Bjorn Helgaas , Simon Horman , Magnus Damm , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Laurent Pinchart , Kieran Bingham , Jacopo Mondi , xu_shunji@hoperun.com Subject: Re: [PATCH 6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes Message-ID: <20191004103227.GR42880@e119886-lin.cambridge.arm.com> References: <1570178133-21532-1-git-send-email-fabrizio.castro@bp.renesas.com> <1570178133-21532-7-git-send-email-fabrizio.castro@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1570178133-21532-7-git-send-email-fabrizio.castro@bp.renesas.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, Oct 04, 2019 at 09:35:32AM +0100, Fabrizio Castro wrote: > This patch adds PCIe{0,1} device nodes for R8A774B1 SoC. > > Signed-off-by: Fabrizio Castro > --- Reviewed-by: Andrew Murray > arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++-- > 1 file changed, 40 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi > index 3bd0b47..0163b284 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi > @@ -1304,19 +1304,57 @@ > }; > > pciec0: pcie@fe000000 { > + compatible = "renesas,pcie-r8a774b1", > + "renesas,pcie-rcar-gen3"; > reg = <0 0xfe000000 0 0x80000>; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x00 0xff>; > - /* placeholder */ > + device_type = "pci"; > + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 > + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 > + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 > + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; > + /* Map all possible DDR as inbound ranges */ > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; > + interrupts = , > + , > + ; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; > + clock-names = "pcie", "pcie_bus"; > + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; > + resets = <&cpg 319>; > + status = "disabled"; > }; > > pciec1: pcie@ee800000 { > + compatible = "renesas,pcie-r8a774b1", > + "renesas,pcie-rcar-gen3"; > reg = <0 0xee800000 0 0x80000>; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x00 0xff>; > - /* placeholder */ > + device_type = "pci"; > + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 > + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 > + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 > + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; > + /* Map all possible DDR as inbound ranges */ > + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; > + interrupts = , > + , > + ; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; > + clock-names = "pcie", "pcie_bus"; > + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; > + resets = <&cpg 318>; > + status = "disabled"; > }; > > fdp1@fe940000 { > -- > 2.7.4 >