From: Christoph Hellwig <hch@infradead.org>
To: Pankaj Dubey <pankaj.dubey@samsung.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
bhelgaas@google.com, andrew.murray@arm.com,
lorenzo.pieralisi@arm.com, gustavo.pimentel@synopsys.com,
jingoohan1@gmail.com, vidyas@nvidia.com,
Anvesh Salveru <anvesh.s@samsung.com>
Subject: Re: [PATCH v3] PCI: dwc: Add support to add GEN3 related equalization quirks
Date: Tue, 15 Oct 2019 01:16:20 -0700 [thread overview]
Message-ID: <20191015081620.GA28204@infradead.org> (raw)
In-Reply-To: <1571108362-25962-1-git-send-email-pankaj.dubey@samsung.com>
On Tue, Oct 15, 2019 at 08:29:22AM +0530, Pankaj Dubey wrote:
> From: Anvesh Salveru <anvesh.s@samsung.com>
>
> In some platforms, PCIe PHY may have issues which will prevent linkup
> to happen in GEN3 or higher speed. In case equalization fails, link will
> fallback to GEN1.
>
> DesignWare controller gives flexibility to disable GEN3 equalization
> completely or only phase 2 and 3 of equalization.
>
> This patch enables the DesignWare driver to disable the PCIe GEN3
> equalization by enabling one of the following quirks:
> - DWC_EQUALIZATION_DISABLE: To disable GEN3 equalization all phases
> - DWC_EQ_PHASE_2_3_DISABLE: To disable GEN3 equalization phase 2 & 3
>
> Platform drivers can set these quirks via "quirk" variable of "dw_pcie"
> struct.
Please submit this together with the changes to the dwc frontend driver
that actually wants to set these quirks.
next prev parent reply other threads:[~2019-10-15 8:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20191015025933epcas5p1f0891dacc13648559ed8e037e49ee5b1@epcas5p1.samsung.com>
2019-10-15 2:59 ` [PATCH v3] PCI: dwc: Add support to add GEN3 related equalization quirks Pankaj Dubey
2019-10-15 8:16 ` Christoph Hellwig [this message]
2019-10-15 8:58 ` Pankaj Dubey
2019-10-15 9:05 ` 'Christoph Hellwig'
2019-10-15 15:17 ` Pankaj Dubey
2019-10-16 6:52 ` 'Christoph Hellwig'
2019-10-16 14:44 ` Jingoo Han
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