From: Bjorn Helgaas <helgaas@kernel.org>
To: "Luís Mendes" <luis.p.mendes@gmail.com>
Cc: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au>,
Linux PCI <linux-pci@vger.kernel.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Jason Cooper <jason@lakedaemon.net>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: Problem with PCIe enumeration of Google/Coral TPU Edge module on Linux
Date: Thu, 9 Apr 2020 11:30:10 -0500 [thread overview]
Message-ID: <20200409163010.GA8879@google.com> (raw)
In-Reply-To: <CAEzXK1oCwx=w3S0ednwM2mJEEidqF3saEKu9OQP=i82y3Az0Aw@mail.gmail.com>
On Thu, Apr 09, 2020 at 04:25:40PM +0100, Luís Mendes wrote:
> Hi Bjorn,
>
> I've good news. I've found the culprit and it is a pretty simple
> issue, however the good solution is not obvious to me.
> Can you help in finding the best way to patch this issue?
>
> So first detailing the problem in file setup_bus.c there is this *if
> condition* to ignore resources from classless devices and so
> it is that this Google/Coral Edge TPU is a classless device with class 0xff:
>
> static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
> {
> u16 class = dev->class >> 8;
>
> pci_info(dev, "%s\n", __func__);
> /* Don't touch classless devices or host bridges or IOAPICs */
> if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
> return;
> ....
>
> So the one possible trivial, non generic, attempt that works is to do:
> static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
> {
> u16 class = dev->class >> 8;
>
> pci_info(dev, "%s\n", __func__);
> /* Don't touch classless devices or host bridges or IOAPICs */
> if ((class == PCI_CLASS_NOT_DEFINED && !(dev->vendor == 0x1ac1 &&
> dev->device==0x089a)) || class == PCI_CLASS_BRIDGE_HOST)
> return;
> ....
>
> What is your suggestion to make the solution generic? Create a
> whitelist? Remove this verification? I have no idea... nothing sounds
> good to me...
Good detective work, thanks for chasing this down!
I should have seen that check when adding the debug. Guess I thought
"sort", hmmm, that just re-orders things without actually changing the
content. But pdev_sort_resources() in fact *adds* resources to a
list, and if resources aren't on the list, we apparently don't assign
space for them.
In any event, I would first check to see if there's an Edge TPU
firmware update that might set the class code.
If not, we should probably add a quirk to override the class code,
similar to quirk_eisa_bridge(), fixup_rev1_53c810(),
fixup_ti816x_class(), quirk_tw686x_class().
Bjorn
next prev parent reply other threads:[~2020-04-09 16:30 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 14:32 Problem with PCIe enumeration of Google/Coral TPU Edge module on Linux Luís Mendes
2020-03-06 21:47 ` Bjorn Helgaas
2020-03-07 12:11 ` Luís Mendes
2020-03-07 15:26 ` Luís Mendes
2020-03-07 21:38 ` Bjorn Helgaas
2020-03-08 5:51 ` Nicholas Johnson
2020-03-09 11:21 ` Luís Mendes
2020-03-11 14:20 ` Luís Mendes
2020-03-29 22:11 ` Luís Mendes
2020-03-30 19:49 ` Bjorn Helgaas
2020-03-31 21:28 ` Luís Mendes
2020-04-01 18:16 ` Bjorn Helgaas
2020-04-01 21:20 ` Luís Mendes
2020-04-01 21:55 ` Luís Mendes
2020-04-01 23:31 ` Bjorn Helgaas
2020-04-02 14:13 ` Luís Mendes
2020-04-04 1:32 ` Bjorn Helgaas
2020-04-04 21:39 ` Luís Mendes
2020-04-08 23:05 ` Luís Mendes
2020-04-09 15:25 ` Luís Mendes
2020-04-09 15:29 ` Luís Mendes
2020-04-09 16:30 ` Bjorn Helgaas [this message]
2020-04-09 17:32 ` Luís Mendes
2020-04-09 18:08 ` Bjorn Helgaas
2020-04-09 20:07 ` Luís Mendes
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