Re: [PATCH v2] PCI: Do not use pcie_get_speed_cap() to determine when to start waiting

[Mika Westerberg <mika.westerberg@linux.intel.com>]

On Fri, May 15, 2020 at 03:53:21PM -0500, Bjorn Helgaas wrote:
> On Fri, May 15, 2020 at 12:55:35PM +0300, Mika Westerberg wrote:
> > On Thu, May 14, 2020 at 05:41:32PM -0500, Bjorn Helgaas wrote:
> > > On Thu, May 14, 2020 at 04:30:43PM +0300, Mika Westerberg wrote:
> > > > Kai-Heng Feng reported that it takes long time (>1s) to resume
> > > > Thunderbolt connected PCIe devices from both runtime suspend and system
> > > > sleep (s2idle).
> > > > 
> > > > These PCIe downstream ports the second link capability (PCI_EXP_LNKCAP2)
> > > > announces support for speeds > 5 GT/s but it is then capped by the
> > > > second link control (PCI_EXP_LNKCTL2) register to 2.5 GT/s. This
> > > > possiblity was not considered in pci_bridge_wait_for_secondary_bus() so
> > > > it ended up waiting for 1100 ms as these ports do not support active
> > > > link layer reporting either.
> > > 
> > > I don't think PCI_EXP_LNKCTL2 is relevant here.  I think the lack of
> > > Data Link Layer Link Active is just a chip erratum.  Is that
> > > documented anywhere?
> > 
> > I think it is relevant because if you hard-code (hardware) LNKCTL2 to
> > always target 2.5GT/s then it effectively does not need to implement
> > data link layer active because the link speed never goes higher than
> > that.
> 
> I don't think it's reasonable to expect software to check Link
> Capabilities 2, then try to write Link Control 2 and figure out
> whether the target speed is hard-wired.  I think these devices
> are just broken (at least per spec).

Software does not need to figure that out. It needs to check this field
if it needs to know the "actual" supported link speed.

Spec specifically allows this:

  The default value of this field is the highest Link speed supported by
  the component (as reported in the Max Link Speed field of the Link
  Capabilities Register) unless the corresponding platform/form factor
  requires a different default value.

and it even allows hardwiring this:

  Components that support only the 2.5 GT/s speed are permitted to
  hardwire this field to 0000b.