From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D966BC433E0 for ; Wed, 10 Jun 2020 10:27:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B27D5206C3 for ; Wed, 10 Jun 2020 10:27:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728194AbgFJK15 convert rfc822-to-8bit (ORCPT ); Wed, 10 Jun 2020 06:27:57 -0400 Received: from relay12.mail.gandi.net ([217.70.178.232]:49669 "EHLO relay12.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726533AbgFJK15 (ORCPT ); Wed, 10 Jun 2020 06:27:57 -0400 Received: from windsurf.home (lfbn-tou-1-915-109.w86-210.abo.wanadoo.fr [86.210.146.109]) (Authenticated sender: thomas.petazzoni@bootlin.com) by relay12.mail.gandi.net (Postfix) with ESMTPSA id 12554200008; Wed, 10 Jun 2020 10:27:50 +0000 (UTC) Date: Wed, 10 Jun 2020 12:27:50 +0200 From: Thomas Petazzoni To: "Shmuel H." Cc: Jason Cooper , Marek =?UTF-8?B?QmVow7pu?= , Baruch Siach , Chris ackham , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH] pci: pci-mvebu: setup BAR0 to internal-regs Message-ID: <20200610122750.389c990f@windsurf.home> In-Reply-To: References: <20200608144024.1161237-1-sh@tkos.co.il> <20200608214335.156baaaa@windsurf> Organization: Bootlin X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hello, On Tue, 9 Jun 2020 14:21:07 +0300 "Shmuel H." wrote: > Unfortunately, there is almost no documentation about the purpose of > this register apart from this cryptic sentence: > >      "BAR0 is dedicated to internal register access" (Marvell a38x > functional docs, section 19.8). > > I can only assume that only specific devices trigger the need for the > PCIe controller to access the SoC's internal registers and therefore > will fail to operate properly. In fact, section 10.2.6 of the Armada XP datasheet, about MSI/MSI-X support gives a hint: in order for the device to do a write to the MSI doorbell address, it needs to write to a register in the "internal registers" space". So it makes a lot of sense that this BAR0 has to be configured. Could you try to boot your system without your patch, and with the pci=nomsi argument on the kernel command line ? This will prevent the driver from using MSI, so it should fallback to legacy IRQs. If that works, then we have the confirmation the issue is MSI related. This will be useful just to have a good commit message that explains the problem, because otherwise I am fine with your patch. Thanks! Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com