From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A96E1C433E0 for ; Wed, 10 Jun 2020 19:20:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7D8CC2072E for ; Wed, 10 Jun 2020 19:20:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728111AbgFJTUm (ORCPT ); Wed, 10 Jun 2020 15:20:42 -0400 Received: from relay12.mail.gandi.net ([217.70.178.232]:58339 "EHLO relay12.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726893AbgFJTUl (ORCPT ); Wed, 10 Jun 2020 15:20:41 -0400 Received: from windsurf.home (lfbn-tou-1-915-109.w86-210.abo.wanadoo.fr [86.210.146.109]) (Authenticated sender: thomas.petazzoni@bootlin.com) by relay12.mail.gandi.net (Postfix) with ESMTPSA id A3EB9200002; Wed, 10 Jun 2020 19:20:38 +0000 (UTC) Date: Wed, 10 Jun 2020 21:20:37 +0200 From: Thomas Petazzoni To: "Shmuel H." Cc: Jason Cooper , Marek =?UTF-8?B?QmVow7pu?= , Baruch Siach , Chris ackham , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH] pci: pci-mvebu: setup BAR0 to internal-regs Message-ID: <20200610212037.7fd32a43@windsurf.home> In-Reply-To: References: <20200608144024.1161237-1-sh@tkos.co.il> <20200608214335.156baaaa@windsurf> Organization: Bootlin X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, 10 Jun 2020 17:17:15 +0300 "Shmuel H." wrote: > Apparently, the PCIe controller is outside of the internal registers space. No, it is not. It is outside of the internal-regs node in the DT because it needs more "ranges" properties, but the PCIe controller registers *are* within the internal registers window: <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 > I could try to use a similar code as in > arch/arm/mach-mvebu/pm.c:mvebu_internal_reg_base or get the first child > of "internal-regs" and call of_translate_address on it with one zero cell. > > Do you have a better solution? In mvebu_pcie_map_registers(), we retrieve the address of the PCIe registers for each port. You can take regs.start, round it down to 1 MB, and you'll get your base address. Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com