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[84.0.113.134]) by smtp.gmail.com with ESMTPSA id f10sm27096310edx.5.2020.07.07.16.03.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2020 16:03:53 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 9/13] PCI: Check return value of pcie_capability_read_*() Date: Wed, 8 Jul 2020 00:03:20 +0200 Message-Id: <20200707220324.8425-10-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200707220324.8425-1-refactormyself@gmail.com> References: <20200707220324.8425-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 13/13, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_word is checked to confirm success. Check the return value of pcie_capability_read_word() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/probe.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f66988cea25..3c87a8a1d4b5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1121,10 +1121,11 @@ EXPORT_SYMBOL(pci_add_new_bus); static void pci_enable_crs(struct pci_dev *pdev) { u16 root_cap = 0; + int ret; /* Enable CRS Software Visibility if supported */ - pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); - if (root_cap & PCI_EXP_RTCAP_CRSVIS) + ret = pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); + if (!ret && (root_cap & PCI_EXP_RTCAP_CRSVIS)) pcie_capability_set_word(pdev, PCI_EXP_RTCTL, PCI_EXP_RTCTL_CRSSVE); } @@ -1519,9 +1520,10 @@ void set_pcie_port_type(struct pci_dev *pdev) void set_pcie_hotplug_bridge(struct pci_dev *pdev) { u32 reg32; + int ret; - pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); - if (reg32 & PCI_EXP_SLTCAP_HPC) + ret = pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); + if (!ret && (reg32 & PCI_EXP_SLTCAP_HPC)) pdev->is_hotplug_bridge = 1; } @@ -2057,10 +2059,11 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign) bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) { u16 v; + int ret; - pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); - return !!(v & PCI_EXP_DEVCTL_RELAX_EN); + return (!ret && !!(v & PCI_EXP_DEVCTL_RELAX_EN)); } EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); @@ -2096,16 +2099,17 @@ static void pci_configure_ltr(struct pci_dev *dev) struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); struct pci_dev *bridge; u32 cap, ctl; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_LTR)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_LTR)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); - if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); + if (!ret && (ctl & PCI_EXP_DEVCTL2_LTR_EN)) { if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { dev->ltr_path = 1; return; @@ -2142,12 +2146,13 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev) struct pci_dev *bridge; int pcie_type; u32 cap; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) return; pcie_type = pci_pcie_type(dev); -- 2.18.2