From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48599C433EB for ; Fri, 10 Jul 2020 14:20:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2290420674 for ; Fri, 10 Jul 2020 14:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728031AbgGJOUk (ORCPT ); Fri, 10 Jul 2020 10:20:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727820AbgGJOUk (ORCPT ); Fri, 10 Jul 2020 10:20:40 -0400 Received: from theia.8bytes.org (8bytes.org [IPv6:2a01:238:4383:600:38bc:a715:4b6d:a889]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E951CC08C5CE; Fri, 10 Jul 2020 07:20:39 -0700 (PDT) Received: by theia.8bytes.org (Postfix, from userid 1000) id 990CB20C; Fri, 10 Jul 2020 16:20:38 +0200 (CEST) Date: Fri, 10 Jul 2020 16:20:37 +0200 From: Joerg Roedel To: Robin Murphy Cc: hch@lst.de, iommu@lists.linux-foundation.org, jonathan.lemon@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, baolu.lu@linux.intel.com, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/2] iommu/intel: Avoid SAC address trick for PCIe devices Message-ID: <20200710142037.GM27672@8bytes.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, Jul 08, 2020 at 12:32:41PM +0100, Robin Murphy wrote: > For devices stuck behind a conventional PCI bus, saving extra cycles at > 33MHz is probably fairly significant. However since native PCI Express > is now the norm for high-performance devices, the optimisation to always > prefer 32-bit addresses for the sake of avoiding DAC is starting to look > rather anachronistic. Technically 32-bit addresses do have shorter TLPs > on PCIe, but unless the device is saturating its link bandwidth with > small transfers it seems unlikely that the difference is appreciable. > > What definitely is appreciable, however, is that the IOVA allocator > doesn't behave all that well once the 32-bit space starts getting full. > As DMA working sets get bigger, this optimisation increasingly backfires > and adds considerable overhead to the dma_map path for use-cases like > high-bandwidth networking. > > As such, let's simply take it out of consideration for PCIe devices. > Technically this might work out suboptimal for a PCIe device stuck > behind a conventional PCI bridge, or for PCI-X devices that also have > native 64-bit addressing, but neither of those are likely to be found > in performance-critical parts of modern systems. > > Signed-off-by: Robin Murphy > --- > drivers/iommu/intel/iommu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Applied both, thanks.