From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3EE2C433DF for ; Mon, 13 Jul 2020 13:14:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE3B9206F0 for ; Mon, 13 Jul 2020 13:14:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729545AbgGMNO3 (ORCPT ); Mon, 13 Jul 2020 09:14:29 -0400 Received: from 8bytes.org ([81.169.241.247]:52542 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729523AbgGMNO3 (ORCPT ); Mon, 13 Jul 2020 09:14:29 -0400 Received: by theia.8bytes.org (Postfix, from userid 1000) id 9B18D36B; Mon, 13 Jul 2020 15:14:27 +0200 (CEST) Date: Mon, 13 Jul 2020 15:14:26 +0200 From: Joerg Roedel To: Robin Murphy Cc: hch@lst.de, iommu@lists.linux-foundation.org, jonathan.lemon@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, baolu.lu@linux.intel.com, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/2] iommu/dma: Avoid SAC address trick for PCIe devices Message-ID: <20200713131426.GQ27672@8bytes.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, Jul 08, 2020 at 12:32:42PM +0100, Robin Murphy wrote: > As for the intel-iommu implementation, relegate the opportunistic > attempt to allocate a SAC address to the domain of conventional PCI > devices only, to avoid it increasingly causing far more performance > issues than possible benefits on modern PCI Express systems. > > Signed-off-by: Robin Murphy > --- > drivers/iommu/dma-iommu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c > index 4959f5df21bd..0ff124f16ad4 100644 > --- a/drivers/iommu/dma-iommu.c > +++ b/drivers/iommu/dma-iommu.c > @@ -426,7 +426,8 @@ static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain, > dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end); > > /* Try to get PCI devices a SAC address */ > - if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) > + if (dma_limit > DMA_BIT_MASK(32) && > + dev_is_pci(dev) && !pci_is_pcie(to_pci_dev(dev))) > iova = alloc_iova_fast(iovad, iova_len, > DMA_BIT_MASK(32) >> shift, false); > Unfortunatly this patch causes XHCI initialization failures on my AMD Ryzen system. I will remove both from the IOMMU tree for now. I guess the XHCI chip in my system does not support full 64bit dma addresses and needs a quirk or something like that. But until this is resolved its better to not change the IOVA allocation behavior. Regards, Joerg