From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC0AEC388F9 for ; Tue, 27 Oct 2020 08:03:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9073B21D24 for ; Tue, 27 Oct 2020 08:03:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="GZzYa62K" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2508679AbgJ0IDp (ORCPT ); Tue, 27 Oct 2020 04:03:45 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18936 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2508680AbgJ0IDk (ORCPT ); Tue, 27 Oct 2020 04:03:40 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Tue, 27 Oct 2020 01:03:19 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 27 Oct 2020 08:03:36 +0000 Received: from vidyas-desktop.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Tue, 27 Oct 2020 08:03:32 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , Subject: [PATCH V2 0/2] Add support to configure DWC for ECRC Date: Tue, 27 Oct 2020 13:33:28 +0530 Message-ID: <20201027080330.8877-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603785799; bh=ZAWrTnsJdsZBg4TX4fkbfnoBs45cYd0AJJa1fauq/mY=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:X-NVConfidentiality: MIME-Version:Content-Type; b=GZzYa62KE36Sso9uw0od7w/l+3Zt2rKtEZyeyZA8l8ijHdfV+oHt/27Bj9owD4JFX jU5wSR8pF1ceZO7TuxjleH/v9RZXHQ9nQDf0tt8D4jwQyk7PlKHFrSGSwpAfAKW1Zu LNitf98aDI1NU6fWzbesjlZge71X8JxhAgsva8ntCN9zPMH9Ye7N+J4cU7k9MV0JCC E1YFVSTlzfoJM8iguStfb9ThfGWb64wsUPBjiE6tHl77EOu+kZtA0xyocEX5SQJ5R1 DklAEQe8nrKGA2eGlQ0Wvf3ixqx+GWWGPTDZvuweuYV5whRQhBDZo7tDMWcedV0eKP f1PAGwDC8rQRA== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This series has two patches. Patch-1: Adds a public API to query if the system has ECRC policty turned on. Patch-2: DesignWare core PCIe IP has a TLP Digest (TD) override bit in one of its control registers of ATU. This bit needs to be programmed for proper ECRC functionality. This is currently identified as an issue with DesignWare IP version 4.90a. DWC code queries the PCIe sub-system through the API added in Patch-1 to find out if ECRC is turned on or not and configures ATU accordingly. V2: * Addressed Jingoo's review comments Vidya Sagar (2): PCI/AER: Add pcie_is_ecrc_enabled() API PCI: dwc: Add support to configure for ECRC drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/pci.h | 2 ++ drivers/pci/pcie/aer.c | 11 +++++++++++ 4 files changed, 20 insertions(+), 2 deletions(-) -- 2.17.1