From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: marek.vasut@gmail.com
Cc: linux-pci@vger.kernel.org,
Marek Vasut <marek.vasut+renesas@gmail.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Wolfram Sang <wsa@the-dreams.de>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH V5] PCI: rcar: Add L1 link state fix into data abort hook
Date: Thu, 15 Apr 2021 17:46:06 +0100 [thread overview]
Message-ID: <20210415164606.GA32085@lpieralisi> (raw)
In-Reply-To: <20210411185030.8818-1-marek.vasut@gmail.com>
On Sun, Apr 11, 2021 at 08:50:30PM +0200, marek.vasut@gmail.com wrote:
[...]
> +#ifdef CONFIG_ARM
> +static DEFINE_SPINLOCK(pmsr_lock);
> +static int rcar_pcie_aarch32_abort_handler(unsigned long addr,
> + unsigned int fsr, struct pt_regs *regs)
> +{
> + unsigned long flags;
> + int ret = 1;
I think we should return 1 only if the condition that triggered
the fault can't be fixed. If it is fixed on another core we
should not return 1 so ret should be set according to the PMSR
register state IIUC.
Lorenzo
> + u32 pmsr;
> +
> + spin_lock_irqsave(&pmsr_lock, flags);
> +
> + if (!pcie_base || !__clk_is_enabled(pcie_bus_clk))
> + goto unlock_exit;
> +
> + pmsr = readl(pcie_base + PMSR);
> +
> + /*
> + * Test if the PCIe controller received PM_ENTER_L1 DLLP and
> + * the PCIe controller is not in L1 link state. If true, apply
> + * fix, which will put the controller into L1 link state, from
> + * which it can return to L0s/L0 on its own.
> + */
> + if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) {
> + writel(L1IATN, pcie_base + PMCTLR);
> + while (!(readl(pcie_base + PMSR) & L1FAEG))
> + ;
> + writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
> + ret = 0;
> + }
> +
> +unlock_exit:
> + spin_unlock_irqrestore(&pmsr_lock, flags);
> + return ret;
> +}
> +
> +static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = {
> + { .compatible = "renesas,pcie-r8a7779" },
> + { .compatible = "renesas,pcie-r8a7790" },
> + { .compatible = "renesas,pcie-r8a7791" },
> + { .compatible = "renesas,pcie-rcar-gen2" },
> + {},
> +};
> +
> +static int __init rcar_pcie_init(void)
> +{
> + if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) {
> +#ifdef CONFIG_ARM_LPAE
> + hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
> + "asynchronous external abort");
> +#else
> + hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
> + "imprecise external abort");
> +#endif
> + }
> +
> + return platform_driver_register(&rcar_pcie_driver);
> +}
> +device_initcall(rcar_pcie_init);
> +#else
> builtin_platform_driver(rcar_pcie_driver);
> +#endif
> diff --git a/drivers/pci/controller/pcie-rcar.h b/drivers/pci/controller/pcie-rcar.h
> index d4c698b5f821..9bb125db85c6 100644
> --- a/drivers/pci/controller/pcie-rcar.h
> +++ b/drivers/pci/controller/pcie-rcar.h
> @@ -85,6 +85,13 @@
> #define LTSMDIS BIT(31)
> #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
> #define PMSR 0x01105c
> +#define L1FAEG BIT(31)
> +#define PMEL1RX BIT(23)
> +#define PMSTATE GENMASK(18, 16)
> +#define PMSTATE_L1 (3 << 16)
> +#define PMCTLR 0x011060
> +#define L1IATN BIT(31)
> +
> #define MACS2R 0x011078
> #define MACCGSPSETR 0x011084
> #define SPCNGRSN BIT(31)
> --
> 2.30.2
>
prev parent reply other threads:[~2021-04-15 16:46 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-11 18:50 [PATCH V5] PCI: rcar: Add L1 link state fix into data abort hook marek.vasut
2021-04-12 12:26 ` Geert Uytterhoeven
2021-04-15 16:46 ` Lorenzo Pieralisi [this message]
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