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Date:   Sun, 18 Jul 2021 23:26:09 +0200
From:   Lukas Wunner <lukas@wunner.de>
To:     stuart hayes <stuart.w.hayes@gmail.com>
Cc:     Bjorn Helgaas <helgaas@kernel.org>,
        Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@linux.intel.com>,
        Dan Williams <dan.j.williams@intel.com>,
        Ethan Zhao <haifeng.zhao@intel.com>,
        Sinan Kaya <okaya@kernel.org>, Ashok Raj <ashok.raj@intel.com>,
        Keith Busch <kbusch@kernel.org>,
        Yicong Yang <yangyicong@hisilicon.com>,
        linux-pci@vger.kernel.org, Russell Currey <ruscur@russell.cc>,
        Oliver OHalloran <oohall@gmail.com>,
        Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH v2] PCI: pciehp: Ignore Link Down/Up caused by DPC
Message-ID: <20210718212609.GA12573@wunner.de>
References: <0be565d97438fe2a6d57354b3aa4e8626952a00b.1619857124.git.lukas@wunner.de>
 <20210616221945.GA3010216@bjorn-Precision-5520>
 <20210620073804.GA13118@wunner.de>
 <08c046b0-c9f2-3489-eeef-7e7aca435bb9@gmail.com>
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On Tue, Jul 06, 2021 at 05:15:02PM -0500, stuart hayes wrote:
> I believe the Link Down is happening because a hot reset is propagated down
> when the link is lost under the root port 64:02.0.  From the PCIe Base Spec
> 5.0, section 6.6.1 "conventional reset":
[...]

Hm, sounds plausible.  Just so that I understand this correctly,
the hotplug port at 0000:68:00.0 is DPC-capable, but the error
that is contained by DPC at the Root Port occurs further up in
the hierarchy, right? (I.e. somewhere above the hotplug port.)

The patch you're using to work around the issue would break if
the hotplug port is *not* DPC-capable.  Yes, yes, I understand
that it's not meant as a real patch, but it shows how tricky
it is to fix the issue.  I need to do a little more thinking
what a proper solution could look like.

Thanks,

Lukas