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From: Lukas Wunner <lukas@wunner.de>
To: Jon Derrick <jonathan.derrick@linux.dev>
Cc: linux-pci@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>,
	Ashok Raj <ashok.raj@intel.com>,
	James Puthukattukaran <james.puthukattukaran@oracle.com>,
	Jon Derrick <jonathan.derrick@intel.com>
Subject: Re: [PATCH v3] PCI: pciehp: Add quirk to handle spurious DLLSC on a x4x4 SSD
Date: Sun, 12 Sep 2021 10:45:47 +0200	[thread overview]
Message-ID: <20210912084547.GA26678@wunner.de> (raw)
In-Reply-To: <20210830155628.130054-1-jonathan.derrick@linux.dev>

On Mon, Aug 30, 2021 at 09:56:28AM -0600, Jon Derrick wrote:
> When an Intel P5608 SSD is bifurcated into x4x4 mode, and the upstream
> ports both support hotplugging on each respective x4 device, a slot
> management system for the SSD requires both x4 slots to have power
> removed via sysfs (echo 0 > slot/N/power), from the OS before it can
> safely turn-off physical power for the whole x8 device. The implications
> are that slot status will display powered off and link inactive statuses
> for the x4 devices where the devices are actually powered until both
> ports have powered off.

Just to get a better understanding, does the P5608 have an internal
PCIe switch with hotplug capability on the Downstream Ports or
does it plug into two separate PCIe slots?  I recall previous patches
mentioned a CEM interposer?  (An lspci listing might be helpful.)


> --- a/drivers/pci/hotplug/pciehp_ctrl.c
> +++ b/drivers/pci/hotplug/pciehp_ctrl.c
> @@ -225,6 +225,7 @@ void pciehp_handle_disable_request(struct controller *ctrl)
>  void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events)
>  {
>  	int present, link_active;
> +	struct pci_dev *pdev = ctrl->pcie->port;

Nit: Reverse christmas tree.


> @@ -265,6 +266,12 @@ void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events)
>  		cancel_delayed_work(&ctrl->button_work);
>  		fallthrough;
>  	case OFF_STATE:
> +		if (pdev->shared_pcc_and_link_slot &&
> +		    (events & PCI_EXP_SLTSTA_DLLSC) && !link_active) {
> +			mutex_unlock(&ctrl->state_lock);
> +			break;
> +		}
> +

I think you also need to add...

			pdev->shared_pcc_and_link_slot = false;

... here to reset the shared_pcc_and_link_slot attribute in case the
next card plugged into the slot doesn't have the quirk.

(This can't be done in pciehp_unconfigure_device() because the attribute
is queried *after* the slot has been brought down.)


> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5750,3 +5750,37 @@ static void apex_pci_fixup_class(struct pci_dev *pdev)
>  }
>  DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
>  			       PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
> +
> +#ifdef CONFIG_HOTPLUG_PCI_PCIE

It's possible to put the quirk at the bottom of pciehp_ctrl.c and
thus avoid the need for the #ifdef here.  (We've got another
pciehp-specific quirk at the bottom of pciehp_hpc.c.)

Otherwise LGTM.

Thanks,

Lukas

  parent reply	other threads:[~2021-09-12  8:45 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-30 15:56 [PATCH v3] PCI: pciehp: Add quirk to handle spurious DLLSC on a x4x4 SSD Jon Derrick
2021-08-30 17:46 ` Raj, Ashok
2021-08-31  1:59 ` jonathan.derrick
2021-09-12  8:45 ` Lukas Wunner [this message]
2021-09-13 21:07   ` Jon Derrick
2021-09-14 14:46     ` Lukas Wunner
2021-09-20 17:18       ` Jon Derrick
2022-07-08 16:35         ` Jonathan Derrick
2022-09-24  7:32           ` Lukas Wunner
2022-09-26 21:05             ` Jonathan Derrick
2022-09-26 21:21             ` Ashok Raj

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