* Revert "PCI/ASPM: Save/restore L1SS Capability for suspend/resume"
@ 2021-09-20 22:11 Hemant Kumar
2021-09-20 22:26 ` Bjorn Helgaas
0 siblings, 1 reply; 2+ messages in thread
From: Hemant Kumar @ 2021-09-20 22:11 UTC (permalink / raw)
To: helgaas; +Cc: linux-pci, manivannan.sadhasivam
Hi Bjorn,
Is there any plan to revisit the fix to allow L1SS CTRL1 and CTRL2 save
and restore to work with suspend and resume.
Referring to the lkml discussion
https://lore.kernel.org/linux-pci/20201228040513.GA611645@bjorn-Precision-5520/
A patch was shared, described as :-
"4257f7e008ea restores PCI_L1SS_CTL1, then PCI_L1SS_CTL2. I think it
should do those in the reverse order, since the Enable bits are in
PCI_L1SS_CTL1. It also restores L1SS state (potentially enabling
L1.x) before we restore the PCIe Capability (potentially enabling ASPM
as a whole). Those probably should also be in the other order."
We are planning to enable aspm driver, but without L1SS control register
save and restore, it gets disabled after resume.
Thanks,
Hemant
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: Revert "PCI/ASPM: Save/restore L1SS Capability for suspend/resume"
2021-09-20 22:11 Revert "PCI/ASPM: Save/restore L1SS Capability for suspend/resume" Hemant Kumar
@ 2021-09-20 22:26 ` Bjorn Helgaas
0 siblings, 0 replies; 2+ messages in thread
From: Bjorn Helgaas @ 2021-09-20 22:26 UTC (permalink / raw)
To: Hemant Kumar; +Cc: linux-pci, manivannan.sadhasivam
On Mon, Sep 20, 2021 at 03:11:30PM -0700, Hemant Kumar wrote:
> Hi Bjorn,
>
> Is there any plan to revisit the fix to allow L1SS CTRL1 and CTRL2 save and
> restore to work with suspend and resume.
>
> Referring to the lkml discussion https://lore.kernel.org/linux-pci/20201228040513.GA611645@bjorn-Precision-5520/
>
> A patch was shared, described as :-
> "4257f7e008ea restores PCI_L1SS_CTL1, then PCI_L1SS_CTL2. I think it
> should do those in the reverse order, since the Enable bits are in
> PCI_L1SS_CTL1. It also restores L1SS state (potentially enabling
> L1.x) before we restore the PCIe Capability (potentially enabling ASPM
> as a whole). Those probably should also be in the other order."
>
> We are planning to enable aspm driver, but without L1SS control register
> save and restore, it gets disabled after resume.
I don't remember the state of that, but if somebody posts a patch to
do the save/restore, and it fixes the problems we saw the first time,
I'm open to merging it.
Bjorn
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-09-20 22:28 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-09-20 22:11 Revert "PCI/ASPM: Save/restore L1SS Capability for suspend/resume" Hemant Kumar
2021-09-20 22:26 ` Bjorn Helgaas
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).