From: Jason Gunthorpe <jgg@ziepe.ca>
To: Haakon Bugge <haakon.bugge@oracle.com>
Cc: Leon Romanovsky <leon@kernel.org>,
Doug Ledford <dledford@redhat.com>,
Bjorn Helgaas <bhelgaas@google.com>,
OFED mailing list <linux-rdma@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: Enabling RO on a VF
Date: Fri, 1 Oct 2021 08:54:55 -0300 [thread overview]
Message-ID: <20211001115455.GJ3544071@ziepe.ca> (raw)
In-Reply-To: <48FF6F8E-95E2-4A29-A059-12EF614B381C@oracle.com>
On Fri, Oct 01, 2021 at 11:05:15AM +0000, Haakon Bugge wrote:
> Hey,
>
>
> Commit 1477d44ce47d ("RDMA/mlx5: Enable Relaxed Ordering by default
> for kernel ULPs") uses pcie_relaxed_ordering_enabled() to check if
> RO can be enabled. This function checks if the Enable Relaxed
> Ordering bit in the Device Control register is set. However, on a
> VF, this bit is RsvdP (Reserved for future RW
> implementations. Register bits are read-only and must return zero
> when read. Software must preserve the value read for writes to
> bits.).
>
> Hence, AFAICT, RO will not be enabled when using a VF.
>
> How can that be fixed?
When qemu takes a VF and turns it into a PF in a VM it must emulate
the RO bit and return one
Jason
next prev parent reply other threads:[~2021-10-01 11:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 11:05 Enabling RO on a VF Haakon Bugge
2021-10-01 11:54 ` Jason Gunthorpe [this message]
2021-10-01 11:59 ` Haakon Bugge
2021-10-01 12:01 ` Jason Gunthorpe
2021-10-05 23:09 ` Si-Wei Liu
2021-10-05 23:28 ` Jason Gunthorpe
2021-10-12 17:57 ` Si-Wei Liu
2021-10-14 22:23 ` Jason Gunthorpe
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