Re: [PATCH 09/13] PCI: aardvark: Implement re-issuing config requests on CRS response

Lorenzo Pieralisi
2021-10-07T11:52:06Z

On Wed, Oct 06, 2021 at 03:13:05PM -0500, Bjorn Helgaas wrote:

[...]

> > We need a way for those PCI controllers to communicate to SW that
> > they actually received a CRS completion (and that they don't retry
> > in HW).
>
> AFAICT this would be controller-dependent. I think some controllers
> have registers that control the number of retries, but of course
> that's completely controller-dependent, too.
>
> > By implementing the logic in the aardvark controller that platform
> > information is there so to the best of my knowledge this patch
> > is sound.
> >
> > I assume that the HW retry is in the specs because there is no
> > architected way if CRS Software Visibility is not enabled/present to
> > report CRS completion in an architected PCI manner but I just
> > don't know the entire background behind this.
>
> I assume an error bit would be set in the Status or Secondary Status
> register when a PCIe transaction fails. I'm not sure anybody *looks*
> at those, though.
>
> This still looks like a PCI controller band-aid for a device or driver
> problem that will likely still exist on other platforms.

Yes that's true. I believe we can merge this patch (?) but it would
also be good if Pali/Marek have time to test on other HW and
maybe generalize the concept.

Lorenzo