Re: [PATCH 06/13] PCI: aardvark: Do not clear status bits of masked interrupts

Marek Behún
2021-10-04T15:18:28Z

On Mon, 4 Oct 2021 15:06:53 +0100
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:

> [+Marc - always better to have his eyes on IRQ handling code]
>
> > - if (!isr0_status && !isr1_status) {
> > - advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
> > - advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
>
> This looks fine - on the other hand if no interrupt is set in the status
> registers (that are filtered with the masks) we are dealing with a
> spurious IRQ right ? Just gauging how severe this is.

Yes, spurious IRQ can really happen.

Patch 7 in this series fixes an issue where aardvark does not mask all
interrupts, and then kernel can think that an interrupt is masked but
it really isn't.

Also, some interrupts may be masked by the user of the emulated bridge
(some other driver), so that they can be polled. But if we clear all of
them in the status, even the masked ones, then the other driver which
is polling will always get a zero.

Marek